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1. 发明申请

WO2005034225A1 A SEMICONDUCTOR DEVICE HAVING A NICKEL/COBALT SILICIDE REGION FORMED IN A SILICON REGION 审中-公开
标题翻译：在硅区形成的镍/钴硅氧化物区域的半导体器件
公开(公告)号：WO2005034225A1
公开(公告)日：2005-04-14
申请号：PCT/US2004/031037
申请日：2004-09-17
申请人： ADVANCED MICRO DEVICES, INC. , KAMMLER, Thorsten , WIECZOREK, Karsten , FRENKEL, Austin
发明人： KAMMLER, Thorsten , WIECZOREK, Karsten , FRENKEL, Austin
IPC分类号： H01L21/285
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665
摘要： By forming a buried nickel silicide layer (260A) followed by a cobalt silicide layer (261A) in silicon containing regions, such as a gate electrode of a field effect transistor, the superior characteristics of both silicides may be combined so as to provide the potential for further device scaling without unduly compromising the sheet resistance and the contact resistance of scaled silicon circuit features.
摘要翻译：通过在含硅区域（例如场效应晶体管的栅电极）中形成掩埋的硅化镍层（260A），随后是硅化钴层（261A），可以组合两种硅化物的优异特性以提供电位用于进一步的器件定标，而不会不适当地损害比例硅电路特征的薄层电阻和接触电阻。

2. 发明申请

WO2009108370A1 AN ETCH STOP LAYER OF REDUCED THICKNESS FOR PATTERNING A DIELECTRIC MATERIAL IN A CONTACT LEVEL OF CLOSELY SPACED TRANSISTORS 审中-公开
标题翻译：用于在绝缘间隔晶体管的接触层中绘制介电材料的减小厚度的蚀刻层
公开(公告)号：WO2009108370A1
公开(公告)日：2009-09-03
申请号：PCT/US2009/001287
申请日：2009-02-27
申请人： ADVANCED MICRO DEVICES, INC. , WIECZOREK, Karsten , HORSTMANN, Manfred , HUEBLER, Peter , RUTTLOFF, Kerstin
发明人： WIECZOREK, Karsten , HORSTMANN, Manfred , HUEBLER, Peter , RUTTLOFF, Kerstin
IPC分类号： H01L21/768 , H01L21/8238
CPC分类号： H01L21/76826 , H01L21/76832 , H01L21/823412 , H01L21/823425 , H01L21/823807 , H01L29/7843 , Y02P80/30
摘要： In a dual stress liner approach, an intermediate etch stop material (234) may be provided on the basis of a plasma-assisted oxidation process (250) rather than by deposition so the corresponding thickness (234T) of the etch stop material (234) may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional strategies, thereby reducing deposition-related irregularities which may translate into a significant reduction of yield loss, in particular for highly scaled semiconductor devices (200).
摘要翻译：在双重应力衬里方法中，可以基于等离子体辅助氧化工艺（250）而不是通过沉积来提供中间蚀刻停止材料（234），使得蚀刻停止材料（234）的对应厚度（234T）可能会减少。因此，与常规策略相比，所产生的纵横比可能不那么明显，从而减少沉积相关的不规则性，这可能转化为产量损失的显着降低，特别是对于高度缩放的半导体器件（200）。

3. 发明申请

WO2006118787A1 A SEMICONDUCTOR DEVICE HAVING A GATE DIELECTRIC OF DIFFERENT BLOCKING CHARACTERISTICS 审中-公开
标题翻译：具有不同阻塞特性的栅极电介质的半导体器件
公开(公告)号：WO2006118787A1
公开(公告)日：2006-11-09
申请号：PCT/US2006/014628
申请日：2006-04-19
申请人： ADVANCED MICRO DEVICES, INC. , WIECZOREK, Karsten , RAAB, Michael , ROMERO, Karla
发明人： WIECZOREK, Karsten , RAAB, Michael , ROMERO, Karla
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462
摘要： By locally adapting the blocking capability of gate insulation layers 205A, 205B for N-channel transistors and P-channel transistors, the reliability and threshold stability of the P-channel transistor may be enhanced, while nevertheless electron mobility of the N-channel transistor may be kept at a high level. This may be accomplished by incorporating a different amount of a dielectric dopant into respective gate insulation layer portions 205A, 205B.
摘要翻译：通过局部地适应用于N沟道晶体管和P沟道晶体管的栅极绝缘层205A，205B的阻挡能力，可以提高P沟道晶体管的可靠性和阈值稳定性，而N沟道晶体管的电子迁移率可能保持在高水平。这可以通过将不同量的电介质掺杂剂并入相应的栅极绝缘层部分205A，205B中来实现。

4. 发明申请

WO2009134412A1 METHOD FOR REDUCING DEFECTS OF GATE OF CMOS DEVICES DURING CLEANING PROCESSES BY MODIFYING A PARASITIC PN JUNCTION 审中-公开
标题翻译：通过修改PARASITIC PN JUNCTION来减少清洁过程中CMOS器件的栅极缺陷的方法
公开(公告)号：WO2009134412A1
公开(公告)日：2009-11-05
申请号：PCT/US2009/002669
申请日：2009-04-30
申请人： ADVANCED MICRO DEVICES, INC. , HORSTMANN, Manfred , JAVORKA, Peter , WIECZOREK, Karsten , RUTTLOFF, Kerstin
发明人： HORSTMANN, Manfred , JAVORKA, Peter , WIECZOREK, Karsten , RUTTLOFF, Kerstin
IPC分类号： H01L21/8238 , H01L21/02
CPC分类号： H01L21/823828 , H01L21/02068 , H01L21/26506 , H01L21/32155 , H01L21/823835 , H01L21/823871
摘要： A method is disclosed which includes implanting an inert species in a layer of a gate electrode material (205A), the gate electrode material being formed above a substrate (201) and having a P-doped layer portion and an N-doped layer portion, forming a first gate electrode (205P) from the P-doped layer portion and a second gate electrode (205N) from the N-doped layer portion, performing a wet chemical cleaning process, and forming a first transistor (200B) on the basis of the first gate electrode (205P) and a second transistor (200A) on the basis of the second gate electrode (205N).
摘要翻译：公开了一种方法，其包括在栅电极材料（205A）的层中注入惰性物质，栅电极材料形成在衬底（201）上方并具有P掺杂层部分和N掺杂层部分，从所述P掺杂层部分形成第一栅电极（205P），从所述N掺杂层部分形成第二栅电极（205N），进行湿化学清洗处理，以及基于基于第二栅电极（205N）的第一栅电极（205P）和第二晶体管（200A）。

5. 发明申请

WO2006022946A1 TECHNIQUE FOR EVALUATING LOCAL ELECTRICAL CHARACTERISTICS IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于评估半导体器件中的局部电气特性的技术
公开(公告)号：WO2006022946A1
公开(公告)日：2006-03-02
申请号：PCT/US2005/018357
申请日：2005-05-25
申请人： ADVANCED MICRO DEVICES, INC. , WIRBELEIT, Frank , BURBACH, Gert , WIECZOREK, Karsten , HORSTMANN, Manfred
发明人： WIRBELEIT, Frank , BURBACH, Gert , WIECZOREK, Karsten , HORSTMANN, Manfred
IPC分类号： H01L23/544
CPC分类号： H01L22/34
摘要： By providing a test structure (100) including a plurality of test pads (104), the anisotropic behavior of stress and strain influenced electrical characteristics, such as the electron mobility, may be determined in a highly efficient manner. Moreover, the test pads (104) may enable the detection of stress and strain induced modifications with a spatial resolution in the order of magnitude of individual circuit elements.
摘要翻译：通过提供包括多个测试焊盘（104）的测试结构（100），可以以高效的方式确定应力和应变影响的电特性（例如电子迁移率）的各向异性行为。此外，测试焊盘（104）可以以单个电路元件的数量级的空间分辨率来检测应力和应变诱发的修改。

6. 发明申请

WO2005017992A1 FIELD EFFECT TRANSISTOR HAVING A DOPED GATE ELECTRODE WITH REDUCED GATE DEPLETION AND METHOD OF FORMING THE TRANSISTOR 审中-公开
标题翻译：具有降低门极截面的多孔栅电极的场效应晶体管和形成晶体管的方法
公开(公告)号：WO2005017992A1
公开(公告)日：2005-02-24
申请号：PCT/US2004/017705
申请日：2004-06-04
申请人： ADVANCED MICRO DEVICES, INC. , WIECZOREK, Karsten , FEUDEL, Thomas , KAMMLER, Thorsten , BUCHHOLTZ, Wolfgang
发明人： WIECZOREK, Karsten , FEUDEL, Thomas , KAMMLER, Thorsten , BUCHHOLTZ, Wolfgang
IPC分类号： H01L21/336
CPC分类号： H01L29/66553 , H01L29/4908 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/78618
摘要： By forming an implantation mask (220) prior to the definition of the drain and the source areas (208), an effective decoupling of the gate dopant concentration from that of the drain and source concentrations is achieved. Moreover, after removal of the implantation mask (220), the lateral dimension of the gate electrode (205) may be defined by well-established sidewall spacer (207) techniques, thereby providing a scaling advantage with respect to conventional approaches based on photolithography and anisotropic etching.
摘要翻译：通过在漏极和源极区域（208）的定义之前形成注入掩模（220），实现了栅极掺杂剂浓度与漏极和源极浓度的有效去耦。此外，在移除注入掩模（220）之后，栅电极（205）的横向尺寸可以通过确定的侧壁间隔物（207）技术来限定，从而相对于基于光刻的常规方法提供缩放优点，各向异性蚀刻。

7. 发明申请

WO2007126907A1 SEMICONDUCTOR DEVICE COMPRISING SOI TRANSISTORS AND BULK TRANSISTORS AND A METHOD OF FORMING THE SAME 审中-公开
标题翻译：包含SOI晶体管和块晶体管的半导体器件及其形成方法
公开(公告)号：WO2007126907A1
公开(公告)日：2007-11-08
申请号：PCT/US2007/007705
申请日：2007-03-30
申请人： ADVANCED MICRO DEVICES, INC. , FEUDEL, Thomas , HORSTMANN, Manfred , WIECZOREK, Karsten , HELLER, Thomas
发明人： FEUDEL, Thomas , HORSTMANN, Manfred , WIECZOREK, Karsten , HELLER, Thomas
IPC分类号： H01L21/84 , H01L27/12 , H01L29/04
CPC分类号： H01L21/84 , H01L21/76251 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/7842
摘要： By forming bulk-like transistors (151B) in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.
摘要翻译：通过在其它SOI基CMOS电路的敏感RAM区域中形成块状晶体管（151B），可以实现有价值的芯片面积的显着节省，因为可以基于体晶体管配置形成RAM区域，从而消除滞后通常可以通过提供增加晶体管宽度的晶体管或通过提供身体纽带来考虑效果。因此，高速切换速度的好处可以保持在诸如CPU内核之类的速度关键电路中，同时可以以高空间效率的方式形成RAM电路。

8. 发明申请

WO2007018780A1 SRAM DEVICES UTILIZING TENSILE-STRESSED STRAIN FILMS 审中-公开
标题翻译：使用拉伸应力片的SRAM器件
公开(公告)号：WO2007018780A1
公开(公告)日：2007-02-15
申请号：PCT/US2006/024680
申请日：2006-06-23
申请人： ADVANCED MICRO DEVICES, INC. , CRAIG, Mark , WIECZOREK, Karsten , HORSTMANN, Manfred
发明人： CRAIG, Mark , WIECZOREK, Karsten , HORSTMANN, Manfred
IPC分类号： H01L27/11
CPC分类号： H01L29/7843 , H01L27/11 , H01L27/1104 , H01L29/78
摘要： SRAM devices utilizing tensile-stressed strain films and methods for fabricating such SRAM devices are provided. An SRAM device (50), in one embodiment, comprises an NFET (54) and a PFET (52) that are electrically coupled and physically isolated. The PFET (52) has a gate region (64), a source region (60), and a drain region (58). A tensile-strained stress film (76) is disposed on the gate region (64) and at least a portion of the source region (60) and the drain region (58) of the PFET (52). A method for fabricating a cell of an SRAM device (50) comprises fabricating an NFET (54) and a PFET (52) overlying a substrate (56). The PFET (52) and the NFET (54) are electrically coupled and are physically isolated. A tensile-strained stress film (76) is deposited on the gate region (64) and at least a portion of the source region (60) and the drain region (58) of the PFET (52).
摘要翻译：提供了使用拉伸应力应变膜的SRAM器件和制造这种SRAM器件的方法。在一个实施例中，SRAM器件（50）包括电耦合和物理隔离的NFET（54）和PFET（52）。 PFET（52）具有栅极区（64），源极区（60）和漏极区（58）。拉伸应变膜（76）设置在栅极区域（64）上以及PFET（52）的源极区域（60）和漏极区域（58）的至少一部分。一种用于制造SRAM器件（50）的单元的方法包括制造覆盖在衬底（56）上的NFET（54）和PFET（52）。 PFET（52）和NFET（54）电耦合并且物理隔离。在栅极区域（64）和PFET（52）的源极区域（60）和漏极区域（58）的至少一部分上沉积拉伸应变膜（76）。

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