专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2006022946A1 TECHNIQUE FOR EVALUATING LOCAL ELECTRICAL CHARACTERISTICS IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于评估半导体器件中的局部电气特性的技术
公开(公告)号：WO2006022946A1
公开(公告)日：2006-03-02
申请号：PCT/US2005/018357
申请日：2005-05-25
申请人： ADVANCED MICRO DEVICES, INC. , WIRBELEIT, Frank , BURBACH, Gert , WIECZOREK, Karsten , HORSTMANN, Manfred
发明人： WIRBELEIT, Frank , BURBACH, Gert , WIECZOREK, Karsten , HORSTMANN, Manfred
IPC分类号： H01L23/544
CPC分类号： H01L22/34
摘要： By providing a test structure (100) including a plurality of test pads (104), the anisotropic behavior of stress and strain influenced electrical characteristics, such as the electron mobility, may be determined in a highly efficient manner. Moreover, the test pads (104) may enable the detection of stress and strain induced modifications with a spatial resolution in the order of magnitude of individual circuit elements.
摘要翻译：通过提供包括多个测试焊盘（104）的测试结构（100），可以以高效的方式确定应力和应变影响的电特性（例如电子迁移率）的各向异性行为。此外，测试焊盘（104）可以以单个电路元件的数量级的空间分辨率来检测应力和应变诱发的修改。

2. 发明申请

WO2009108370A1 AN ETCH STOP LAYER OF REDUCED THICKNESS FOR PATTERNING A DIELECTRIC MATERIAL IN A CONTACT LEVEL OF CLOSELY SPACED TRANSISTORS 审中-公开
标题翻译：用于在绝缘间隔晶体管的接触层中绘制介电材料的减小厚度的蚀刻层
公开(公告)号：WO2009108370A1
公开(公告)日：2009-09-03
申请号：PCT/US2009/001287
申请日：2009-02-27
申请人： ADVANCED MICRO DEVICES, INC. , WIECZOREK, Karsten , HORSTMANN, Manfred , HUEBLER, Peter , RUTTLOFF, Kerstin
发明人： WIECZOREK, Karsten , HORSTMANN, Manfred , HUEBLER, Peter , RUTTLOFF, Kerstin
IPC分类号： H01L21/768 , H01L21/8238
CPC分类号： H01L21/76826 , H01L21/76832 , H01L21/823412 , H01L21/823425 , H01L21/823807 , H01L29/7843 , Y02P80/30
摘要： In a dual stress liner approach, an intermediate etch stop material (234) may be provided on the basis of a plasma-assisted oxidation process (250) rather than by deposition so the corresponding thickness (234T) of the etch stop material (234) may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional strategies, thereby reducing deposition-related irregularities which may translate into a significant reduction of yield loss, in particular for highly scaled semiconductor devices (200).
摘要翻译：在双重应力衬里方法中，可以基于等离子体辅助氧化工艺（250）而不是通过沉积来提供中间蚀刻停止材料（234），使得蚀刻停止材料（234）的对应厚度（234T）可能会减少。因此，与常规策略相比，所产生的纵横比可能不那么明显，从而减少沉积相关的不规则性，这可能转化为产量损失的显着降低，特别是对于高度缩放的半导体器件（200）。

3. 发明申请

WO2006022915A1 SELF-BIASING TRANSISTOR STRUCTURE AND SRAM CELL 审中-公开
标题翻译：自偏转晶体管结构和SRAM单元
公开(公告)号：WO2006022915A1
公开(公告)日：2006-03-02
申请号：PCT/US2005/015294
申请日：2005-04-29
申请人： ADVANCED MICRO DEVICES, INC. , WIRBELEIT, Frank , HORSTMANN, Manfred , HOBERT, Christian
发明人： WIRBELEIT, Frank , HORSTMANN, Manfred , HOBERT, Christian
IPC分类号： H01L29/78
CPC分类号： G11C11/412 , H01L27/11
摘要： By providing a self-biasing semiconductor switch, an SRAM cell (450) having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor (400) that allows the formation of an SRAM cell (450) with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.
摘要翻译：通过提供自偏压半导体开关，可以实现具有减少数量的各个有源元件的SRAM单元（450）。在特定实施例中，自偏置半导体器件可以以双通道场效应晶体管（400）的形式提供，其允许形成具有小于六个晶体管元件的SRAM单元（450），并且在优选实施例中，只有两个单独的晶体管元件。

4. 发明申请

WO2008042144A2 A SEMICONDUCTOR DEVICE COMPRISING ISOLATION TRENCHES INDUCING DIFFERENT TYPES OF STRAIN 审中-公开
标题翻译：包含不同类型菌株的分离条件的半导体器件
公开(公告)号：WO2008042144A2
公开(公告)日：2008-04-10
申请号：PCT/US2007/020598
申请日：2007-09-24
申请人： ADVANCED MICRO DEVICES, INC. , SCHWAN, Christoph , BLOOMQUIST, Joe , JAVORKA, Peter , HORSTMANN, Manfred , BEYER, Sven , FORSBERG, Markus , WIRBELEIT, Frank , ROMERO, Karla
发明人： SCHWAN, Christoph , BLOOMQUIST, Joe , JAVORKA, Peter , HORSTMANN, Manfred , BEYER, Sven , FORSBERG, Markus , WIRBELEIT, Frank , ROMERO, Karla
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/7846
摘要： By forming isolation trenches (102 A, 102B) of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions (105A, 105B) may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material (107A, 107B) including compressive and tensile stress may be appropriately provided in the respective isolation trenches (102A, 102B) in order to correspondingly adapt the charge carrier mobility of respective channel regions (121 A, 121B).
摘要翻译：通过基于分离的工艺顺序形成不同类型的固有应力的隔离沟槽（102A，102B），可以调节相邻的有源半导体区域（105A，105B）的应变特性以获得整体器件性能。例如，可以在相应的隔离沟槽（102A，102B）中适当地提供包括压应力和拉伸应力的高应力电介质填充材料（107A，107B），以便相应地适应相应通道区域（121A，121B）的载流子迁移率）。

5. 发明申请

WO2009134412A1 METHOD FOR REDUCING DEFECTS OF GATE OF CMOS DEVICES DURING CLEANING PROCESSES BY MODIFYING A PARASITIC PN JUNCTION 审中-公开
标题翻译：通过修改PARASITIC PN JUNCTION来减少清洁过程中CMOS器件的栅极缺陷的方法
公开(公告)号：WO2009134412A1
公开(公告)日：2009-11-05
申请号：PCT/US2009/002669
申请日：2009-04-30
申请人： ADVANCED MICRO DEVICES, INC. , HORSTMANN, Manfred , JAVORKA, Peter , WIECZOREK, Karsten , RUTTLOFF, Kerstin
发明人： HORSTMANN, Manfred , JAVORKA, Peter , WIECZOREK, Karsten , RUTTLOFF, Kerstin
IPC分类号： H01L21/8238 , H01L21/02
CPC分类号： H01L21/823828 , H01L21/02068 , H01L21/26506 , H01L21/32155 , H01L21/823835 , H01L21/823871
摘要： A method is disclosed which includes implanting an inert species in a layer of a gate electrode material (205A), the gate electrode material being formed above a substrate (201) and having a P-doped layer portion and an N-doped layer portion, forming a first gate electrode (205P) from the P-doped layer portion and a second gate electrode (205N) from the N-doped layer portion, performing a wet chemical cleaning process, and forming a first transistor (200B) on the basis of the first gate electrode (205P) and a second transistor (200A) on the basis of the second gate electrode (205N).
摘要翻译：公开了一种方法，其包括在栅电极材料（205A）的层中注入惰性物质，栅电极材料形成在衬底（201）上方并具有P掺杂层部分和N掺杂层部分，从所述P掺杂层部分形成第一栅电极（205P），从所述N掺杂层部分形成第二栅电极（205N），进行湿化学清洗处理，以及基于基于第二栅电极（205N）的第一栅电极（205P）和第二晶体管（200A）。

6. 发明申请

WO2008121327A1 METHOD OF FORMING A SEMICONDUCTOR STRUCTURE 审中-公开
标题翻译：形成半导体结构的方法
公开(公告)号：WO2008121327A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/004066
申请日：2008-03-28
申请人： ADVANCED MICRO DEVICES, INC. , WIRBELEIT, Frank , STEPHAN, Rolf , HORSTMANN, Manfred
发明人： WIRBELEIT, Frank , STEPHAN, Rolf , HORSTMANN, Manfred
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L21/28123 , H01L29/66545 , H01L29/6659
摘要： A method of forming a semiconductor structure (300) comprises providing a semiconductor substrate (201). A feature (306) is formed over the substrate (201). The feature (306) is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion (212, 213) of the substrate (201) adjacent the feature (306) is performed. The length (330) of the feature (306) in the lateral direction is reduced. After the reduction of the length (330) of the feature (306), a second ion implantation process adapted to introduce second dopant ions into at least one portion (209, 210) of the substrate (201) adjacent the feature (306) is performed. The feature (306) may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate (201).
摘要翻译：形成半导体结构（300）的方法包括提供半导体衬底（201）。在衬底（201）上形成特征（306）。特征（306）在横向上基本上是均匀的。执行适于将第一掺杂剂离子引入邻近特征（306）的衬底（201）的至少一个部分（212,213）中的第一离子注入工艺。特征（306）在横向上的长度（330）减小。在特征（306）的长度（330）减小之后，适于将第二掺杂离子引入邻近特征（306）的衬底（201）的至少一部分（209,210）中的第二离子注入工艺是执行。特征（306）可以是形成在半导体衬底（201）上的场效应晶体管的栅电极。

7. 发明申请

WO2007126907A1 SEMICONDUCTOR DEVICE COMPRISING SOI TRANSISTORS AND BULK TRANSISTORS AND A METHOD OF FORMING THE SAME 审中-公开
标题翻译：包含SOI晶体管和块晶体管的半导体器件及其形成方法
公开(公告)号：WO2007126907A1
公开(公告)日：2007-11-08
申请号：PCT/US2007/007705
申请日：2007-03-30
申请人： ADVANCED MICRO DEVICES, INC. , FEUDEL, Thomas , HORSTMANN, Manfred , WIECZOREK, Karsten , HELLER, Thomas
发明人： FEUDEL, Thomas , HORSTMANN, Manfred , WIECZOREK, Karsten , HELLER, Thomas
IPC分类号： H01L21/84 , H01L27/12 , H01L29/04
CPC分类号： H01L21/84 , H01L21/76251 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/7842
摘要： By forming bulk-like transistors (151B) in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.
摘要翻译：通过在其它SOI基CMOS电路的敏感RAM区域中形成块状晶体管（151B），可以实现有价值的芯片面积的显着节省，因为可以基于体晶体管配置形成RAM区域，从而消除滞后通常可以通过提供增加晶体管宽度的晶体管或通过提供身体纽带来考虑效果。因此，高速切换速度的好处可以保持在诸如CPU内核之类的速度关键电路中，同时可以以高空间效率的方式形成RAM电路。

8. 发明申请

WO2007018780A1 SRAM DEVICES UTILIZING TENSILE-STRESSED STRAIN FILMS 审中-公开
标题翻译：使用拉伸应力片的SRAM器件
公开(公告)号：WO2007018780A1
公开(公告)日：2007-02-15
申请号：PCT/US2006/024680
申请日：2006-06-23
申请人： ADVANCED MICRO DEVICES, INC. , CRAIG, Mark , WIECZOREK, Karsten , HORSTMANN, Manfred
发明人： CRAIG, Mark , WIECZOREK, Karsten , HORSTMANN, Manfred
IPC分类号： H01L27/11
CPC分类号： H01L29/7843 , H01L27/11 , H01L27/1104 , H01L29/78
摘要： SRAM devices utilizing tensile-stressed strain films and methods for fabricating such SRAM devices are provided. An SRAM device (50), in one embodiment, comprises an NFET (54) and a PFET (52) that are electrically coupled and physically isolated. The PFET (52) has a gate region (64), a source region (60), and a drain region (58). A tensile-strained stress film (76) is disposed on the gate region (64) and at least a portion of the source region (60) and the drain region (58) of the PFET (52). A method for fabricating a cell of an SRAM device (50) comprises fabricating an NFET (54) and a PFET (52) overlying a substrate (56). The PFET (52) and the NFET (54) are electrically coupled and are physically isolated. A tensile-strained stress film (76) is deposited on the gate region (64) and at least a portion of the source region (60) and the drain region (58) of the PFET (52).
摘要翻译：提供了使用拉伸应力应变膜的SRAM器件和制造这种SRAM器件的方法。在一个实施例中，SRAM器件（50）包括电耦合和物理隔离的NFET（54）和PFET（52）。 PFET（52）具有栅极区（64），源极区（60）和漏极区（58）。拉伸应变膜（76）设置在栅极区域（64）上以及PFET（52）的源极区域（60）和漏极区域（58）的至少一部分。一种用于制造SRAM器件（50）的单元的方法包括制造覆盖在衬底（56）上的NFET（54）和PFET（52）。 PFET（52）和NFET（54）电耦合并且物理隔离。在栅极区域（64）和PFET（52）的源极区域（60）和漏极区域（58）的至少一部分上沉积拉伸应变膜（76）。

9. 发明申请

WO2007100589A1 TRANSISTOR DEVICE HAVING AN INCREASED THRESHOLD STABILITY WITHOUT DRIVE CURRENT DEGRADATION 审中-公开
标题翻译：具有无驱动电流降低的增加的阈值稳定性的晶体管器件
公开(公告)号：WO2007100589A1
公开(公告)日：2007-09-07
申请号：PCT/US2007/004544
申请日：2007-02-20
申请人： ADVANCED MICRO DEVICES, INC. , WEI, Andy , KAMMLER, Thorsten , HOENTSCHEL, Jan , HORSTMANN, Manfred
发明人： WEI, Andy , KAMMLER, Thorsten , HOENTSCHEL, Jan , HORSTMANN, Manfred
IPC分类号： H01L21/336 , H01L29/10 , H01L29/08
CPC分类号： H01L29/0847 , H01L21/26586 , H01L29/1045 , H01L29/1083 , H01L29/66492 , H01L29/665 , H01L29/66636 , H01L29/7848
摘要： By removing a portion of a halo region (206, 306) or by avoiding the formation of the halo region (206, 306) within the extension region (209A), which may be subsequently formed on the basis of a re-grown semiconductor material (218, 318), the threshold roll off behavior may be significantly improved, wherein an enhanced current drive capability may simultaneously be achieved.
摘要翻译：通过去除一部分卤素区域（206,306）或通过避免在扩展区域（209A）内形成卤区域（206,306），其可以随后基于重新生长的半导体材料形成（218,318），可以显着改善阈值滚降行为，其中可以同时实现增强的电流驱动能力。

10. 发明申请

WO2006049834A1 A SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR REGIONS HAVING DIFFERENTLY STRAINED CHANNEL REGIONS AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：包括具有不同应变通道区域的半导体区域的半导体器件及其制造方法
公开(公告)号：WO2006049834A1
公开(公告)日：2006-05-11
申请号：PCT/US2005/036779
申请日：2005-10-12
申请人： ADVANCED MICRO DEVICES, INC. , HORSTMANN, Manfred , PRUEFER, Ekkehard , BUCHHOLTZ, Wolfgang
发明人： HORSTMANN, Manfred , PRUEFER, Ekkehard , BUCHHOLTZ, Wolfgang
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/265
CPC分类号： H01L29/6659 , H01L21/265 , H01L21/26506 , H01L21/823807 , H01L21/84 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： By locally modifying the intrinsic stress of a dielectric layer laterally enclosing gate electrode structures of a transistor configuration formed in accordance with in-laid gate techniques, the charge carrier mobility of different transistor elements may individually be adjusted. In particular, in in-laid gate structure transistor architecture, NMOS transistors and PMOS transistors may receive a tensile and a compressive stress, respectively.
摘要翻译：通过局部改变根据叠层栅极技术形成的晶体管配置的横向包围栅电极结构的电介质层的固有应力，可以单独地调节不同晶体管元件的电荷载流子迁移率。特别地，在嵌入式栅结构晶体管架构中，NMOS晶体管和PMOS晶体管可以分别接收拉伸和压缩应力。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式