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1. 发明授权

US07217648B2 Post-ESL porogen burn-out for copper ELK integration 有权
标题翻译：用于铜ELK整合的后ESL致孔剂烧尽
公开(公告)号：US07217648B2
公开(公告)日：2007-05-15
申请号：US11020372
申请日：2004-12-22
申请人： Yung-Cheng Lu , Ying-Tsung Chen , Zhen-Cheng Wu , Pi-Tsung Chen
发明人： Yung-Cheng Lu , Ying-Tsung Chen , Zhen-Cheng Wu , Pi-Tsung Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02304 , H01L21/0234 , H01L21/02362 , H01L21/3122 , H01L21/3148 , H01L21/31695 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76846 , H01L21/7685 , H01L2221/1047
摘要： A method of manufacturing a semiconductor device having a porous, low-k dielectric layer is provided. A preferred embodiment comprises the steps of forming a porogen-containing, low-k dielectric layer, in the damascene process. In preferred embodiments, pore generation, by e-beam porogen degradation, occurs after the steps of CMP planarizing the damascene copper conductor and depositing a semipermeable cap layer. In alternative embodiments, the cap layer consists essentially of silicon carbide, silicon nitride, Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof. The semipermeable cap layer is preferably deposited under PECVD conditions such that the cap layer is sufficiently permeable to enable removal of porogen degradation by-products. Preferred embodiments further include an in-situ N2/NH3 treatment before depositing the semipermeable cap layer.
摘要翻译：提供一种制造具有多孔低k电介质层的半导体器件的方法。优选的实施方案包括在镶嵌工艺中形成含致孔剂的低k电介质层的步骤。在优选的实施方案中，通过电子束致孔剂降解的孔产生在CMP平坦化镶嵌铜导体并沉积半透膜盖层的步骤之后发生。在替代实施例中，盖层基本上由碳化硅，氮化硅，Co，W，Al，Ta，Ti，Ni，Ru及其组合组成。半透膜盖层优选在PECVD条件下沉积，使得盖层具有足够的可渗透性以能够除去致孔剂降解副产物。优选实施方案还包括在沉积半透膜盖层之前的原位N 2 / NH 3 N 3处理。

2. 发明申请

US20060134906A1 Post-ESL porogen burn-out for copper ELK integration 有权
标题翻译：用于铜ELK整合的后ESL致孔剂烧尽
公开(公告)号：US20060134906A1
公开(公告)日：2006-06-22
申请号：US11020372
申请日：2004-12-22
申请人： Yung-Cheng Lu , Ying-Tsung Chen , Zhen-Cheng Wu , Pi-Tsung Chen
发明人： Yung-Cheng Lu , Ying-Tsung Chen , Zhen-Cheng Wu , Pi-Tsung Chen
IPC分类号： H01L21/76
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02304 , H01L21/0234 , H01L21/02362 , H01L21/3122 , H01L21/3148 , H01L21/31695 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76846 , H01L21/7685 , H01L2221/1047
摘要： A method of manufacturing a semiconductor device having a porous, low-k dielectric layer is provided. A preferred embodiment comprises the steps of forming a porogen-containing, low-k dielectric layer, in the damascene process. In preferred embodiments, pore generation, by e-beam porogen degradation, occurs after the steps of CMP planarizing the damascene copper conductor and depositing a semipermeable cap layer. In alternative embodiments, the cap layer consists essentially of silicon carbide, silicon nitride, Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof. The semipermeable cap layer is preferably deposited under PECVD conditions such that the cap layer is sufficiently permeable to enable removal of porogen degradation by-products. Preferred embodiments further include an in-situ N2/NH3 treatment before depositing the semipermeable cap layer.
摘要翻译：提供一种制造具有多孔低k电介质层的半导体器件的方法。优选的实施方案包括在镶嵌工艺中形成含致孔剂的低k电介质层的步骤。在优选的实施方案中，通过电子束致孔剂降解的孔产生在CMP平坦化镶嵌铜导体并沉积半透膜盖层的步骤之后发生。在替代实施例中，盖层基本上由碳化硅，氮化硅，Co，W，Al，Ta，Ti，Ni，Ru及其组合组成。半透膜盖层优选在PECVD条件下沉积，使得盖层具有足够的可渗透性以能够除去致孔剂降解副产物。优选实施方案还包括在沉积半透膜盖层之前的原位N 2 / NH 3 N 3处理。

3. 发明授权

US07834405B2 Semiconductor device including I/O oxide and nitrided core oxide on substrate 有权
标题翻译：在衬底上包括I / O氧化物和氮化核心氧化物的半导体器件
公开(公告)号：US07834405B2
公开(公告)日：2010-11-16
申请号：US11181915
申请日：2005-07-15
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
IPC分类号： H01L29/76
CPC分类号： H01L21/823462 , H01L27/088 , Y10S438/981
摘要： A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.
摘要翻译：半导体器件包括半导体衬底，其中半导体衬底包括用于核心电路的核心区域和用于外围电路的外围区域。半导体器件在核心区域中的半导体衬底上具有核心氧化物，核心氧化物的一部分被氮化，核心氧化物上的第一多晶硅图案，在周边区域中的半导体衬底上的纯氧化物的I / O氧化物，以及I / O氧化物上的第二多晶硅图案。

4. 发明申请

US20070249164A1 METHOD OF FABRICATING AN INTERCONNECT STRUCTURE 审中-公开
标题翻译：制作互连结构的方法
公开(公告)号：US20070249164A1
公开(公告)日：2007-10-25
申请号：US11379384
申请日：2006-04-20
申请人： Pi-Tsung Chen , Zhen-Cheng Wu , Ying-Tsung Chen , Yung-Cheng Lu
发明人： Pi-Tsung Chen , Zhen-Cheng Wu , Ying-Tsung Chen , Yung-Cheng Lu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76825 , H01L21/76813 , H01L21/76829
摘要： An interconnect structure for a semiconductor device is provided. The interconnect structure for a semiconductor device comprises a substrate having a conductive region thereon, a first dielectric layer having a modified surface portion serving as an etch stop layer and a second dielectric layer having a hardness less than that of the modified surface portion. The interconnect structure for a semiconductor device further comprises a trench-shaped conductive line disposed within the second dielectric layer and a conductive plug disposed within the first dielectric layer and interposed between the trench-shaped conductive line and the conductive region.
摘要翻译：提供了一种用于半导体器件的互连结构。半导体器件的互连结构包括其上具有导电区域的衬底，具有用作蚀刻停止层的改性表面部分的第一介电层和硬度小于改性表面部分的硬度的第二电介质层。用于半导体器件的互连结构还包括设置在第二介电层内的沟槽状导电线和设置在第一电介质层内的介于沟槽状导电线与导电区之间的导电插塞。

5. 发明申请

US20110081758A1 Semiconductor device including I/O oxide nitrided core oxide on substrate, and method of manufacture 有权
标题翻译：在衬底上包括I / O氧化物氮化核心氧化物的半导体器件及其制造方法
公开(公告)号：US20110081758A1
公开(公告)日：2011-04-07
申请号：US12923889
申请日：2010-10-13
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , H01L27/088 , Y10S438/981
摘要： A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.
摘要翻译：半导体器件包括半导体衬底，其中半导体衬底包括用于核心电路的核心区域和用于外围电路的外围区域。半导体器件在核心区域中的半导体衬底上具有核心氧化物，核心氧化物的一部分被氮化，核心氧化物上的第一多晶硅图案，在周边区域中的半导体衬底上的纯氧化物的I / O氧化物，以及I / O氧化物上的第二多晶硅图案。

6. 发明授权

US07247571B2 Method for planarizing semiconductor structures 有权
公开(公告)号：US07247571B2
公开(公告)日：2007-07-24
申请号：US11226979
申请日：2005-09-15
申请人： Ying-Tsung Chen , Yung-Cheng Lu , Zhen-Cheng Wu , Pi-Tsung Chen
发明人： Ying-Tsung Chen , Yung-Cheng Lu , Zhen-Cheng Wu , Pi-Tsung Chen
IPC分类号： H01L21/311
CPC分类号： H01L21/31053 , H01L22/20
摘要： A method for planarizing a semiconductor structure is disclosed. A semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density lower than the first pattern density, is provided. A first dielectric layer is formed above the semiconductor for covering the trenches in the first and second areas. A first chemical mechanical polishing is performed on the first dielectric layer using a predetermined type of slurry for reducing a thickness thereof. The first dielectric layer is then rinsed. A second chemical mechanical polishing is performed on the first dielectric layer using the predetermined type of slurry for further removing the first dielectric layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas.

7. 发明申请

US20070013009A1 Semiconductor device including I/O oxide and nitrided core oxide on substrate, and method of manufacture 有权
标题翻译：在衬底上包括I / O氧化物和氮化核心氧化物的半导体器件及其制造方法
公开(公告)号：US20070013009A1
公开(公告)日：2007-01-18
申请号：US11181915
申请日：2005-07-15
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
IPC分类号： H01L29/78 , H01L21/8234
CPC分类号： H01L21/823462 , H01L27/088 , Y10S438/981
摘要： A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.
摘要翻译：半导体器件包括半导体衬底，其中半导体衬底包括用于核心电路的核心区域和用于外围电路的外围区域。半导体器件在核心区域中的半导体衬底上具有核心氧化物，核心氧化物的一部分被氮化，核心氧化物上的第一多晶硅图案，在周边区域中的半导体衬底上的纯氧化物的I / O氧化物，以及I / O氧化物上的第二多晶硅图案。

8. 发明授权

US08084328B2 Semiconductor device including I/O oxide nitrided core oxide on substrate 有权
标题翻译：在衬底上包括I / O氧化物氮化核心氧化物的半导体器件
公开(公告)号：US08084328B2
公开(公告)日：2011-12-27
申请号：US12923889
申请日：2010-10-13
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
IPC分类号： H01I21/8234
CPC分类号： H01L21/823462 , H01L27/088 , Y10S438/981
摘要： A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.
摘要翻译：半导体器件包括半导体衬底，其中半导体衬底包括用于核心电路的芯区域和用于外围电路的外围区域。半导体器件在核心区域中的半导体衬底上具有核心氧化物，核心氧化物的一部分被氮化，核心氧化物上的第一多晶硅图案，在周边区域中的半导体衬底上的纯氧化物的I / O氧化物，以及I / O氧化物上的第二多晶硅图案。

9. 发明申请

US20070054494A1 Method for planarizing semiconductor structures 有权
标题翻译：半导体结构平面化方法
公开(公告)号：US20070054494A1
公开(公告)日：2007-03-08
申请号：US11226979
申请日：2005-09-15
申请人： Ying-Tsung Chen , Yung-Cheng Lu , Zhen-Cheng Wu , Pi-Tsung Chen
发明人： Ying-Tsung Chen , Yung-Cheng Lu , Zhen-Cheng Wu , Pi-Tsung Chen
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31053 , H01L22/20
摘要： A method for planarizing a semiconductor structure is disclosed. A semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density lower than the first pattern density, is provided. A first dielectric layer is formed above the semiconductor for covering the trenches in the first and second areas. A first chemical mechanical polishing is performed on the first dielectric layer using a predetermined type of slurry for reducing a thickness thereof. The first dielectric layer is then rinsed. A second chemical mechanical polishing is performed on the first dielectric layer using the predetermined type of slurry for further removing the first dielectric layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas.
摘要翻译：公开了一种用于平面化半导体结构的方法。提供具有第一区域的半导体衬底，其中以第一图案密度形成一个或多个沟槽，以及第二区域，其中以比第一图案密度低的第二图案密度形成一个或多个沟槽。第一介电层形成在半导体上方，用于覆盖第一和第二区域中的沟槽。使用用于减小其厚度的预定类型的浆料在第一介电层上进行第一化学机械抛光。然后冲洗第一介电层。使用预定类型的浆料在第一介电层上进行第二化学机械抛光，用于进一步去除沟槽外的第一介电层，从而降低第一和第二区域的表面之间的台阶高度变化。

10. 发明申请

US20060125102A1 Back end of line integration scheme 审中-公开
标题翻译：后端整合方案
公开(公告)号：US20060125102A1
公开(公告)日：2006-06-15
申请号：US11012406
申请日：2004-12-15
申请人： Zhen-Cheng Wu , Ying-Tsung Chen , Pi-Tsung Chen , Yung-Cheng Lu
发明人： Zhen-Cheng Wu , Ying-Tsung Chen , Pi-Tsung Chen , Yung-Cheng Lu
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/7682 , H01L23/5329 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure comprises: a first inter-layer dielectric (ILD) over a substrate; a first metal layer; a plurality of second ILDs over the first ILD; and a plurality of second metal layers, each of the second metal layers is over one of the second ILDs. The first ILD is not cured. It has a k value of between about 2.5 and about 3.0, a pore size of smaller than about 10 Å, and a hardness of greater than about 1.5 Gpa. The second ILDs are cured therefore having lower k values of smaller than about 2.5, pore sizes of greater than about 10 Å, and hardness of smaller than about 1.5 Gpa. The semiconductor structure has reduced plasma charge damage from plasma curing.
摘要翻译：半导体结构包括：在衬底上的第一层间电介质（ILD）; 第一金属层; 在第一ILD上的多个第二ILD; 以及多个第二金属层，每个第二金属层位于第二ILD之一上。第一个ILD没有治愈。其k值为约2.5至约3.0，孔径小于约10埃，硬度大于约1.5Gpa。因此，第二ILD被固化，因此具有小于约2.5，小于约10埃的孔径和小于约1.5Gpa的硬度的较低k值。半导体结构降低了等离子体固化所产生的等离子体电荷损伤。

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