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    • 9. 发明申请
    • Method for planarizing semiconductor structures
    • 半导体结构平面化方法
    • US20070054494A1
    • 2007-03-08
    • US11226979
    • 2005-09-15
    • Ying-Tsung ChenYung-Cheng LuZhen-Cheng WuPi-Tsung Chen
    • Ying-Tsung ChenYung-Cheng LuZhen-Cheng WuPi-Tsung Chen
    • H01L21/302H01L21/461
    • H01L21/31053H01L22/20
    • A method for planarizing a semiconductor structure is disclosed. A semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density lower than the first pattern density, is provided. A first dielectric layer is formed above the semiconductor for covering the trenches in the first and second areas. A first chemical mechanical polishing is performed on the first dielectric layer using a predetermined type of slurry for reducing a thickness thereof. The first dielectric layer is then rinsed. A second chemical mechanical polishing is performed on the first dielectric layer using the predetermined type of slurry for further removing the first dielectric layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas.
    • 公开了一种用于平面化半导体结构的方法。 提供具有第一区域的半导体衬底,其中以第一图案密度形成一个或多个沟槽,以及第二区域,其中以比第一图案密度低的第二图案密度形成一个或多个沟槽。 第一介电层形成在半导体上方,用于覆盖第一和第二区域中的沟槽。 使用用于减小其厚度的预定类型的浆料在第一介电层上进行第一化学机械抛光。 然后冲洗第一介电层。 使用预定类型的浆料在第一介电层上进行第二化学机械抛光,用于进一步去除沟槽外的第一介电层,从而降低第一和第二区域的表面之间的台阶高度变化。