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1. 发明申请

US20120319071A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20120319071A1
公开(公告)日：2012-12-20
申请号：US13495650
申请日：2012-06-13
申请人： Nobuyoshi AWAYA , Takahiro SHIBUYA , Takashi NAKANO , Yoshiaki TABUCHI , Yushi INOUE , Yukio TAMAI
发明人： Nobuyoshi AWAYA , Takahiro SHIBUYA , Takashi NAKANO , Yoshiaki TABUCHI , Yushi INOUE , Yukio TAMAI
IPC分类号： H01L45/00
CPC分类号： G11C13/0007 , G11C2213/79 , H01L27/2436 , H01L45/08 , H01L45/146 , H01L45/1616
摘要： The present invention provides a variable resistive element that can perform a stable switching operation at low voltage and low current, and also provides a low-power consumption large-capacity non-volatile semiconductor memory device including the variable resistive element. The non-volatile semiconductor memory device is a device using a variable resistive element, which includes a variable resistor between a first electrode and a second electrode, for storing information, wherein an oxygen concentration of a hafnium oxide (HfOx) film or a zirconium oxide (ZrOx) film constituting the variable resistor is optimized such that a stoichiometric composition ratio x of oxygen to Hf or Zr falls within a range of 1.7≦x≦1.97.
摘要翻译：本发明提供了一种可在低电压和低电流下进行稳定的开关操作的可变电阻元件，并且还提供包括可变电阻元件的低功耗大容量非易失性半导体存储器件。非易失性半导体存储器件是使用可变电阻元件的器件，其包括用于存储信息的第一电极和第二电极之间的可变电阻器，其中氧化铪（HfO x）膜或氧化锆优选构成可变电阻器的（ZrO x）膜，使得氧与Hf或Zr的化学计量组成比x落在1.7

2. 发明授权

US06251805B1 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06251805B1
公开(公告)日：2001-06-26
申请号：US08993681
申请日：1997-12-18
申请人： Takahisa Yamaha , Yushi Inoue
发明人： Takahisa Yamaha , Yushi Inoue
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , H01L21/02134 , H01L21/02282 , H01L21/02337 , H01L21/31051 , H01L21/3124 , H01L21/316
摘要： A hydrogen silsesquloxane resin film is formed flat by spin-coating or another such method on the surface of a semiconductor substrate or another such treatment wafer 38, after which the above-mentioned resin film is subjected to a heat treatment in an inert gas atmosphere to form a silicon oxide film of preceramic phase. In a hot plate type of heating apparatus, the wafer 38 is placed on a conveyor belt 34 and moved above a heat-generating block 30, which heats the wafer in the open air and converts the preceramic-phase silicon oxide film into a ceramic-phase silicon oxide film. The silane generated during heating does not adhere to the wafer surface as SiO2 particles, so no microscopic protrusions are produced. N2 or another such inert gas may be blown at the wafer 38 during heating.
摘要翻译：在半导体基板或另一个这样的处理晶片38的表面上，通过旋涂或其他这种方法将氢硅倍半酚树脂膜平坦地形成，之后将上述树脂膜在惰性气体气氛中进行热处理形成前陶瓷相的氧化硅膜。在热板式加热装置中，将晶片38放置在输送带34上并移动到发热块30上方，该发热块30在露天加热晶片，并将陶瓷前氧化硅膜转换为陶瓷 - 相氧化硅膜。在加热过程中产生的硅烷作为SiO 2颗粒不粘附到晶片表面，因此不产生微观突起。在加热期间，可以在晶片38上吹入N 2或另一种这样的惰性气体。

3. 发明授权

US5885857A Semiconductor chip capable of suppressing cracks in the insulating layer 失效
标题翻译：能够抑制绝缘层的裂纹的半导体芯片
公开(公告)号：US5885857A
公开(公告)日：1999-03-23
申请号：US7619
申请日：1998-01-15
申请人： Takahisa Yamaha , Yushi Inoue , Masaru Naito
发明人： Takahisa Yamaha , Yushi Inoue , Masaru Naito
IPC分类号： H01L23/52 , H01L21/316 , H01L21/3205 , H01L21/768 , H01L23/31 , H01L23/522 , H01L21/283 , H01L21/306 , H01L21/311
CPC分类号： H01L23/3171 , H01L2924/0002
摘要： A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.
摘要翻译：一种树脂模制半导体器件，其具有布线层和包括SOG膜的层间绝缘层，能够抑制由于热应力引起的SOG膜中的裂纹的产生。在半导体芯片的外周区域中，在包括SOG膜的层间绝缘层中形成通孔，以显着减少残留的SOG膜。作为包含SOG膜的层间绝缘层的下层，形成虚拟布线图案，以使虚拟布线图案上的SOG膜变薄。也可以通过使用较高级布线层，埋入通孔并接触下层虚拟布线图案来形成虚拟布线图案。

4. 发明授权

US08450145B2 Nonvolatile semiconductor memory device and method for producing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08450145B2
公开(公告)日：2013-05-28
申请号：US12939640
申请日：2010-11-04
申请人： Yushi Inoue
发明人： Yushi Inoue
IPC分类号： H01L21/00
CPC分类号： H01L45/04 , G11C13/0007 , H01L27/2436 , H01L27/2472 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1625 , H01L45/1633
摘要： A first opening and a second opening are formed at the same time over a first metal wiring and a second metal wiring, respectively which are provided as the same layer on a substrate on which a transistor for selecting a memory cell is formed. Then, a variable resistor and an upper electrode are deposited on a whole surface so as to completely fill the first opening with the upper electrode but not to completely fill the second opening with it. Thereafter, a variable resistive element is formed in the first opening and a via hole to connect to the third metal wiring (bit line), in the second opening, at the same time, by performing back-etching until a surface of the second metal wiring is exposed at a bottom of the second opening.
摘要翻译：在第一金属布线和第二金属布线上同时形成第一开口和第二开口，第一金属布线和第二金属布线在形成用于选择存储单元的晶体管的基板上设置为同一层。然后，在整个表面上沉积可变电阻器和上电极，以便用上电极完全填充第一开口，但是不能完全填充第二开口。此后，通过进行逆蚀刻，在第一开口中形成可变电阻元件和通孔，以在第二开口中同时连接到第三金属布线（位线），直到第二金属的表面布线暴露在第二开口的底部。

5. 发明申请

US20120261837A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120261837A1
公开(公告)日：2012-10-18
申请号：US13178093
申请日：2011-07-07
申请人： Yushi INOUE , Yukitoshi Hirose
发明人： Yushi INOUE , Yukitoshi Hirose
IPC分类号： H01L23/52
CPC分类号： H01L23/49838 , H01L23/3128 , H01L23/64 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01033 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor device may include, but is not limited to: a wiring hoard; and first and second chips stacked over the wiring board. The wiring board includes a plurality of first data terminals and a plurality of second data terminals. One of the first and second chips is sandwiched between the wiring board and the other of the first and second chips. The first chip includes a plurality of first data pads. The second chip includes a plurality of second data pads and a plurality of third data pads. The first data terminals of the wiring board are electrically connected respectively to the first data pads of the first chip and further respectively to the second data pads of the second chip. The second data terminals are electrically connected respectively to the third data pads of the second chip and electrically disconnected from the first chip.
摘要翻译：半导体器件可以包括但不限于：布线板; 以及堆叠在布线板上的第一和第二芯片。布线板包括多个第一数据终端和多个第二数据终端。第一和第二芯片中的一个夹在布线板和第一和第二芯片中的另一个之间。第一芯片包括多个第一数据焊盘。第二芯片包括多个第二数据焊盘和多个第三数据焊盘。布线板的第一数据端子分别电连接到第一芯片的第一数据焊盘，并且进一步分别连接到第二芯片的第二数据焊盘。第二数据端子分别电连接到第二芯片的第三数据焊盘，并与第一芯片电断开。

6. 发明申请

US20120025163A1 NON-VOLATILE SEMICONDUCTOR DEVICE 有权
标题翻译：非挥发性半导体器件
公开(公告)号：US20120025163A1
公开(公告)日：2012-02-02
申请号：US13182696
申请日：2011-07-14
申请人： Junya ONISHI , Shinobu Yamazaki , Kazuya Ishihara , Yushi Inoue , Yukio Tamai , Nobuyoshi Awaya
发明人： Junya ONISHI , Shinobu Yamazaki , Kazuya Ishihara , Yushi Inoue , Yukio Tamai , Nobuyoshi Awaya
IPC分类号： H01L45/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146
摘要： A variable resistance element that can stably perform a switching operation with a property variation being reduced by suppressing a sharp current that accompanies completion of forming process, and a non-volatile semiconductor memory device including the variable resistance element are realized. The non-volatile semiconductor memory device uses the variable resistance element for storing information in which a resistance changing layer is interposed between a first electrode and a second electrode, and a buffer layer is inserted between the first electrode and the resistance changing layer where a switching interface is formed. The buffer layer and the resistance changing layer include n-type metal oxides, and materials of the buffer layer and the resistance changing layer are selected such that energy at a bottom of a conduction band of the n-type metal oxide configuring the buffer layer is lower than that of the n-type metal oxide configuring the resistance changing layer.
摘要翻译：通过抑制伴随着成形处理的完成的尖锐电流，可以稳定地进行具有特性变化的开关动作的可变电阻元件，以及包括该可变电阻元件的非易失性半导体存储器件。非易失性半导体存储器件使用可变电阻元件来存储在第一电极和第二电极之间插入电阻变化层的信息，并且缓冲层插入在第一电极和电阻变化层之间，其中开关界面形成。缓冲层和电阻变化层包括n型金属氧化物，并且选择缓冲层和电阻变化层的材料，使得构成缓冲层的n型金属氧化物的导带的底部的能量为低于构成电阻变化层的n型金属氧化物。

7. 发明申请

US20050118833A1 Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20050118833A1
公开(公告)日：2005-06-02
申请号：US10998782
申请日：2004-11-30
申请人： Kazumasa Mitsumune , Tsukasa Doi , Yushi Inoue , Kenichirou Abe , Takanori Sonoda
发明人： Kazumasa Mitsumune , Tsukasa Doi , Yushi Inoue , Kenichirou Abe , Takanori Sonoda
IPC分类号： H01L23/522 , H01L21/31 , H01L21/314 , H01L21/318 , H01L21/768 , H01L21/469
CPC分类号： H01L21/02129 , H01L21/0217 , H01L21/02274 , H01L21/3144 , H01L21/3145 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76837
摘要： It is an object of the present invention to provide a method for manufacturing a semiconductor device suppressing the occurrence of voids in an insulating film. A method for manufacturing a semiconductor device according to the present invention comprises the steps of: (1) forming an insulating film 11 composed of a thin silicon nitride film on a semiconductor substrate 1 having at least a necessary element and a recessed part 6 so as to cover the recessed part 6; (2) modifying the surface of the insulating film 11; and (3) forming a BPSG film 15 as an interlayer insulation film on the insulating film. The occurrence of voids in the interlayer insulation film 15 is suppressed by the process for modifying the surface.
摘要翻译：本发明的目的是提供一种制造半导体器件的方法，该半导体器件抑制绝缘膜中空隙的发生。根据本发明的制造半导体器件的方法包括以下步骤：（1）在具有至少必需元件的半导体衬底1上形成由氮化硅薄膜构成的绝缘膜11，以及凹入部分6，以便覆盖凹部6; （2）改性绝缘膜11的表面; 和（3）在绝缘膜上形成作为层间绝缘膜的BPSG膜15。通过改变表面的方法来抑制层间绝缘膜15中的空隙的发生。

8. 发明授权

US5904576A Method of forming wiring structure 失效
标题翻译：形成布线结构的方法
公开(公告)号：US5904576A
公开(公告)日：1999-05-18
申请号：US961276
申请日：1997-10-30
申请人： Takahisa Yamaha , Yushi Inoue
发明人： Takahisa Yamaha , Yushi Inoue
IPC分类号： H01L21/3205 , H01L21/312 , H01L21/316 , H01L21/768 , H01L23/522 , H01L21/31
CPC分类号： H01L21/76801 , H01L21/316 , H01L21/76804 , H01L21/76826 , H01L21/76828
摘要： After wiring patterns are formed on an insulating film covering the surface of a substrate, an insulating film such as plasma CVD SiO.sub.2 is formed covering the wiring patterns. A hydrogen silsesquioxane resin film with a flat surface is formed by spin coating or the like on the insulating film. Thereafter, the resin film is changed into a pre-ceramic silicon oxide film by performing heat treatment in an inert gas atmosphere. On this pre-ceramic silicon oxide film, an insulating film such as plasma enhanced CVD SiO.sub.2 film is formed and another wiring layer is formed on the insulating film. This method of forming a multi-layer wiring structure allows an interlayer insulating film to be planarized, and improves a yield of wiring formation.
摘要翻译：在覆盖基板的表面的绝缘膜上形成布线图案之后，形成覆盖布线图案的等离子体CVD SiO 2等绝缘膜。通过在绝缘膜上旋涂等形成具有平坦表面的氢倍半硅氧烷树脂薄膜。此后，通过在惰性气体气氛中进行热处理将树脂膜变成预陶瓷氧化硅膜。在该预陶瓷氧化硅膜上形成等离子体增强CVD SiO 2膜等绝缘膜，在绝缘膜上形成另一配线层。这种形成多层布线结构的方法允许层间绝缘膜平坦化，并且提高布线形成的产量。

9. 发明授权

US5821162A Method of forming multi-layer wiring utilizing SOG 失效
标题翻译：使用SOG形成多层布线的方法
公开(公告)号：US5821162A
公开(公告)日：1998-10-13
申请号：US679738
申请日：1996-07-12
申请人： Takahisa Yamaha , Yushi Inoue
发明人： Takahisa Yamaha , Yushi Inoue
IPC分类号： H01L21/3205 , H01L21/316 , H01L21/768 , H01L23/538 , H01L21/4763
CPC分类号： H01L21/76801 , H01L21/316 , H01L21/76828
摘要： On a first insulating film covering a substrate, wiring layer patterns are formed. Thereafter, a second insulating film of plasma CVD--SiO.sub.2 or the like is formed thereon. A hydrogen silsesquioxane resin film having a flat surface is spin-coated on the second insulating film. Thereafter, the resin film is subjected to a first heat treatment in an inert gas atmosphere to convert the resin film into a silicon oxide film of a preceramic phase. This preceramic silicon oxide film is subjected to a second heat treatment in an oxidizing atmosphere to convert this preceramic silicon oxide film into a silicon oxide film of a ceramic phase. In this case, a fine size projection is generated on the surface of the ceramic silicon oxide film. On the ceramic silicon oxide film, a third insulating film of plasma CVD--PSG or the like is formed which does not reflect the fine size projection. Thereafter, a fourth insulating film of plasma CVD--SiO.sub.2 is formed, followed by formation of a second wiring layer. It is possible to planarize an interlevel insulating film and improve a process yield.
摘要翻译：在覆盖基板的第一绝缘膜上形成布线层图案。此后，在其上形成等离子体CVD-SiO 2等的第二绝缘膜。将具有平坦表面的氢倍半硅氧烷树脂膜旋涂在第二绝缘膜上。然后，在惰性气体气氛中对树脂膜进行第一次热处理，将树脂膜转换成陶瓷相的氧化硅膜。该氧化硅陶瓷氧化膜在氧化气氛中进行第二次热处理，将该陶瓷氧化硅膜转化为陶瓷相的氧化硅膜。在这种情况下，在陶瓷氧化硅膜的表面上产生细小的投射。在陶瓷氧化硅膜上形成等离子体CVD-PSG等的第三绝缘膜，其不反映微细尺寸的投影。此后，形成等离子体CVD-SiO 2的第四绝缘膜，然后形成第二布线层。可以平坦化层间绝缘膜并提高工艺成品率。

10. 发明授权

US5763936A Semiconductor chip capable of supressing cracks in insulating layer 失效
标题翻译：半导体芯片能够抑制绝缘层的裂纹
公开(公告)号：US5763936A
公开(公告)日：1998-06-09
申请号：US637227
申请日：1996-04-24
申请人： Takahisa Yamaha , Yushi Inoue , Masaru Naito
发明人： Takahisa Yamaha , Yushi Inoue , Masaru Naito
IPC分类号： H01L23/52 , H01L21/316 , H01L21/3205 , H01L21/768 , H01L23/31 , H01L23/522 , H01L23/58 , H01L23/48 , H01L23/544
CPC分类号： H01L23/3171 , H01L2924/0002
摘要： A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.
摘要翻译：一种树脂模制半导体器件，其具有布线层和包括SOG膜的层间绝缘层，能够抑制由于热应力引起的SOG膜中的裂纹的产生。在半导体芯片的外周区域中，在包括SOG膜的层间绝缘层中形成通孔，以显着减少残留的SOG膜。作为包含SOG膜的层间绝缘层的下层，形成虚拟布线图案，以使虚拟布线图案上的SOG膜变薄。也可以通过使用较高级布线层，埋入通孔并接触下层虚拟布线图案来形成虚拟布线图案。

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