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1. 发明申请

US20110089395A1 STRUCTURE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件的结构和制造方法
公开(公告)号：US20110089395A1
公开(公告)日：2011-04-21
申请号：US12976113
申请日：2010-12-22
申请人： Tetsuya OHNISHI , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
发明人： Tetsuya OHNISHI , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
IPC分类号： H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.
摘要翻译：具有交叉点结构的半导体存储器件包括沿一个方向延伸的多个上电极和布置成沿与上电极的一个方向成直角的另一方向延伸的多个下电极。记录材料设置在上电极和下电极之间用于存储数据。记忆材料由钙钛矿材料制成，并且布置在沿着相应的上电极延伸的相应上电极的下电极侧。

2. 发明申请

US20100284237A1 KNEADING APPARATUS 有权
标题翻译：打字机
公开(公告)号：US20100284237A1
公开(公告)日：2010-11-11
申请号：US12733980
申请日：2008-09-10
申请人： Yusuke Takemoto , Keiichi Takahashi , Takahiro Shibuya
发明人： Yusuke Takemoto , Keiichi Takahashi , Takahiro Shibuya
IPC分类号： B01F7/04
CPC分类号： B01F7/042 , B01F3/1221 , B01F7/003 , B01F7/00425 , B01F7/022
摘要： A plurality of paddles Pn (n=1 to 17) is provided on an external periphery of a rotary shaft 3 so as to be arranged helically at a predetermined angular pitch of 90°, and a plurality of paddles Qn is provided on an external periphery of a rotary shaft 4 so as to be arranged helically at a predetermined angular pitch of 72°. The rotary shafts 3, 4 are made to rotate in opposite directions at unequal speeds to convey an object to be kneaded in one conveying direction along the rotary shafts 3, 4 while being kneaded by the paddles. The paddle surfaces of the paddles have either a normal phase for advancing the kneaded object in a feed direction or a reverse phase, and the paddles are arranged so that phases cyclically repeat in the sequence “normal, normal, reverse” in the axial direction of the rotary shafts. Since the kneaded object is pushed back by the reverse phase paddles in the direction opposite to the conveying direction, the stirring action can be performed numerous times, and sufficient and uniform kneading is made possible.
摘要翻译：在旋转轴3的外周设置多个桨叶Pn（n = 1〜17），以规定的90°角度间隔螺旋地配置，在外周设置多个桨叶Qn 旋转轴4以预定的间距为72°螺旋地配置。旋转轴3,4以不相等的速度在相反的方向上旋转，以便在通过桨搅拌的同时沿着旋转轴3,4在一个输送方向上输送待捏合的物体。桨叶的桨叶表面具有用于在捏合物体的进给方向或反相中推进的正相，并且桨叶被布置成使得相位沿轴向方向“正常，正常，反向”的顺序循环重复旋转轴。由于捏合物被反相片沿与输送方向相反的方向推回，因此可以进行多次搅拌作用，并且可以进行足够均匀的捏合。

3. 发明申请

US20060102943A1 Structure and manufacturing method of semiconductor memory device 有权
标题翻译：半导体存储器件的结构和制造方法
公开(公告)号：US20060102943A1
公开(公告)日：2006-05-18
申请号：US11274258
申请日：2005-11-16
申请人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
发明人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
IPC分类号： H01L29/94
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.
摘要翻译：具有交叉点结构的半导体存储器件包括沿一个方向延伸的多个上电极和布置成沿与上电极的一个方向成直角的另一方向延伸的多个下电极。记录材料设置在上电极和下电极之间用于存储数据。记忆材料由钙钛矿材料制成，并且布置在沿着相应的上电极延伸的相应上电极的下电极侧。

4. 发明授权

US08497492B2 Variable resistive element, and its manufacturing method 有权
公开(公告)号：US08497492B2
公开(公告)日：2013-07-30
申请号：US12298818
申请日：2007-02-23
申请人： Yasunari Hosoi , Kazuya Ishihara , Takahiro Shibuya , Tetsuya Ohnishi , Takashi Nakano
发明人： Yasunari Hosoi , Kazuya Ishihara , Takahiro Shibuya , Tetsuya Ohnishi , Takashi Nakano
IPC分类号： H01L47/00
CPC分类号： H01L45/1253 , H01L27/101 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/1273 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1616 , H01L45/1625 , H01L45/1633 , H01L45/1691
摘要： A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element.

5. 发明授权

US08030695B2 Structure and manufacturing method of semiconductor memory device 有权
公开(公告)号：US08030695B2
公开(公告)日：2011-10-04
申请号：US12976113
申请日：2010-12-22
申请人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
发明人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
IPC分类号： H01L21/02
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.

6. 发明授权

US07879626B2 Structure and manufacturing method of semiconductor memory device 有权
标题翻译：半导体存储器件的结构和制造方法
公开(公告)号：US07879626B2
公开(公告)日：2011-02-01
申请号：US11274258
申请日：2005-11-16
申请人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
发明人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
IPC分类号： H01L21/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.
摘要翻译：具有交叉点结构的半导体存储器件包括沿一个方向延伸的多个上电极和布置成沿与上电极的一个方向成直角的另一方向延伸的多个下电极。记录材料设置在上电极和下电极之间用于存储数据。记忆材料由钙钛矿材料制成，并且布置在沿着相应的上电极延伸的相应上电极的下电极侧。

7. 发明申请

US20090200640A1 VARIABLE RESISTIVE ELEMENT, AND ITS MANUFACTURING METHOD 有权
标题翻译：可变电阻元件及其制造方法
公开(公告)号：US20090200640A1
公开(公告)日：2009-08-13
申请号：US12298818
申请日：2007-02-23
申请人： Yasunari Hosoi , Kazuya Ishihara , Takahiro Shibuya , Tetsuya Ohnishi , Takashi Nakano
发明人： Yasunari Hosoi , Kazuya Ishihara , Takahiro Shibuya , Tetsuya Ohnishi , Takashi Nakano
IPC分类号： H01L29/8605 , H01L21/02 , H01L45/00
CPC分类号： H01L45/1253 , H01L27/101 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/1273 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1616 , H01L45/1625 , H01L45/1633 , H01L45/1691
摘要： A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element.
摘要翻译：提供一种可变电阻元件，其包括可变电阻体的电赋能区的面积比由上电极或下电极约束的面积更小的构造及其制造方法。凸起电极材料形成在布置在基底基板上的下电极上。突起电极材料在与下电极的接触面不同的表面与可变电阻体接触。可变电阻体与不同于凸块电极材料的接触表面的表面与上电极接触。因此，凸起电极材料（可变电阻体）与上部电极之间的交叉点区域成为可变电阻体的电性区域，与现有的变量区域相比，能够减小面积电阻元件。

8. 发明申请

US20090096568A1 VARIABLE RESISTANCE ELEMENT, AND ITS MANUFACTURING METHOD 有权
标题翻译：可变电阻元件及其制造方法
公开(公告)号：US20090096568A1
公开(公告)日：2009-04-16
申请号：US12298089
申请日：2007-02-16
申请人： Yasunari Hosoi , Kazuya Ishihara , Takahiro Shibuya , Tetsuya Ohnishi , Takashi Nakano
发明人： Yasunari Hosoi , Kazuya Ishihara , Takahiro Shibuya , Tetsuya Ohnishi , Takashi Nakano
IPC分类号： H01C7/10 , H01C13/02
CPC分类号： H01L27/101 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/124 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1633 , H01L45/1691 , Y10T29/49082
摘要： Provided are a variable resistive element having a configuration that the area of an electrically contributing region in a variable resistor body is smaller than the area defined by an upper electrode or a lower electrode, and a method for manufacturing the variable resistive element. The cross section of a current path, in which an electric current flows through between the two electrodes via the variable resistor body at the time of applying the voltage pulse to between the two electrodes, is formed with a line width of narrower than that of any of the two electrodes and of smaller than a minimum work dimension regarding manufacturing processes, so that its area can be made smaller than that of the electrically contributing region in the variable resistive element of the prior art.
摘要翻译：提供了一种可变电阻元件，其具有可变电阻体中的电赋值区域小于由上电极或下电极限定的面积的构造，以及制造可变电阻元件的方法。在将电压脉冲施加到两个电极之间时，通过可变电阻体在两个电极之间流过电流的电流路径的横截面形成为比任何电极的线宽窄的线宽并且小于关于制造工艺的最小工作尺寸，使得其面积可以比现有技术的可变电阻元件中的电赋值区的面积小。

9. 发明授权

US4271513A Method and apparatus for carrying out loopback test 失效
标题翻译：进行环回测试的方法和装置
公开(公告)号：US4271513A
公开(公告)日：1981-06-02
申请号：US37383
申请日：1979-05-09
申请人： Hiroshi Maejima , Noriaki Fujimura , Takahiro Shibuya , Shigeyuki Akagi
发明人： Hiroshi Maejima , Noriaki Fujimura , Takahiro Shibuya , Shigeyuki Akagi
IPC分类号： G06F11/22 , G06F13/00 , H04B17/40 , H04L1/24 , H04L5/22 , H04L29/14 , G06F11/00
CPC分类号： H04L1/24 , H04B17/406
摘要： The present invention discloses a method for carrying out a loopback test in a data communication system having a first data communication station, a second data communication station and a transmission line connected therebetween. The first data communication station transmits a succession of a first pseudo-random noise signal, a loopback test signal and a second pseudo-random noise signal to the second data communication station by utilizing a usual information data channel, and requires no special channel for carrying out the loopback test. When the second data communication station detects the first pseudo-random noise signal, it transmits the loopback test signal to the first data communication station in order to check the coincidence of the transmitted and the received loopback test signals. The second pseudo-random noise signal denotes the end of the loopback test.
摘要翻译：本发明公开了一种在具有连接在其间的第一数据通信站，第二数据通信站和传输线的数据通信系统中进行环回测试的方法。第一数据通信站通过利用通常的信息数据信道将第一伪随机噪声信号，环回测试信号和第二伪随机噪声信号的序列发送到第二数据通信站，并且不需要用于承载的特殊信道进行环回测试。当第二数据通信站检测到第一伪随机噪声信号时，它将环回测试信号发送到第一数据通信站，以便检查所发送的和所接收的环回测试信号的一致性。第二伪随机噪声信号表示环回测试的结束。

10. 发明申请

US20060154417A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20060154417A1
公开(公告)日：2006-07-13
申请号：US11330806
申请日：2006-01-11
申请人： Naoyuki Shinmura , Shigeo Ohnishi , Tetsuya Ohnishi , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri
发明人： Naoyuki Shinmura , Shigeo Ohnishi , Tetsuya Ohnishi , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri
IPC分类号： H01L21/8242
CPC分类号： H01L45/1675 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641
摘要： The present invention is directed towards a method of manufacturing a semiconductor memory device arranged of a cross point memory array having memory elements provided between upper and lower electrodes for storage of data. The present invention comprises a lower electrode lines forming step of planarizing each of the lower electrode lines and insulating layers provided on both sides of the lower electrode line so as to be substantially uniform in the height thus for patterning the lower electrode lines, a memory element layer depositing step of depositing on the lower electrode lines a memory element layer for the memory elements, and an annealing step of annealing with heat treatment either between the lower electrode lines forming step and the memory element layer depositing step or after the memory element layer depositing step so that any damages caused by the polishing of the surface of the lower electrode lines can be eliminated.
摘要翻译：本发明涉及一种制造半导体存储器件的方法，该半导体存储器件被布置成具有设置在上部和下部电极之间的存储元件的交叉点存储器阵列，用于存储数据。本发明包括下电极线，其形成步骤：将设置在下电极线两侧的每个下电极线和绝缘层平坦化，以使其高度大致均匀，从而构图下电极线;存储元件在下电极线上沉积用于存储元件的存储元件层的层沉积步骤，以及在下电极线形成步骤和存储元件层沉积步骤之间或在存储元件层沉积之后进行热处理退火的退火步骤使得可以消除由下电极线的表面的抛光引起的任何损坏。

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