专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07295457B2 Integrated circuit chip with improved array stability 失效
标题翻译：集成电路芯片具有改进的阵列稳定性
公开(公告)号：US07295457B2
公开(公告)日：2007-11-13
申请号：US10950940
申请日：2004-09-27
申请人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
发明人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C8/08 , G11C11/412 , G11C11/417
摘要： A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.
摘要翻译：可以由多个电源提供的多阈值集成电路（IC），具有诸如阵列静态随机存取存储器（SRAM）单元的锁存器阵列和具有改进的稳定性和减小的亚阈值泄漏的CMOS SRAM。阵列单元中的选定器件（NFET和/或PFET）和支持逻辑，例如在数据通路和非关键逻辑中，都适用于较低的栅极和亚阈值泄漏。正常基极FET具有基极阈值，并且定制的FET具有高于阈值。在多电源芯片中，具有定制FET的电路由增加的电源电压供电。

2. 发明授权

US07787284B2 Integrated circuit chip with improved array stability 有权
标题翻译：集成电路芯片具有改进的阵列稳定性
公开(公告)号：US07787284B2
公开(公告)日：2010-08-31
申请号：US12133450
申请日：2008-06-05
申请人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
发明人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C8/08 , G11C11/412 , G11C11/417
摘要： A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.
摘要翻译：可以由多个电源提供的多阈值集成电路（IC），具有诸如阵列静态随机存取存储器（SRAM）单元的锁存器阵列和具有改进的稳定性和减小的亚阈值泄漏的CMOS SRAM。阵列单元中的选定器件（NFET和/或PFET）和支持逻辑，例如在数据通路和非关键逻辑中，都适用于较低的栅极和亚阈值泄漏。正常基极FET具有基极阈值，并且定制的FET具有高于阈值。在多电源芯片中，具有定制FET的电路由增加的电源电压供电。

3. 发明授权

US07173875B2 SRAM array with improved cell stability 有权
标题翻译：具有改善电池稳定性的SRAM阵列
公开(公告)号：US07173875B2
公开(公告)日：2007-02-06
申请号：US10950928
申请日：2004-09-27
申请人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
发明人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
IPC分类号： G11C8/00 , G11C11/00
CPC分类号： G11C11/413 , G11C8/08
摘要： A CMOS static random access memory (SRAM) cell array, an integrated chip including the array and a method of accessing cells in the array with improved cell stability. Bit lines connected to half selected cells in the array are floated during cell accesses for improved cell stability.
摘要翻译： CMOS静态随机存取存储器（SRAM）单元阵列，包括该阵列的集成芯片以及一种以更好的单元稳定性访问阵列中的单元的方法。连接到阵列中的一半选定单元的位线在单元访问期间浮动以改善单元稳定性。

4. 发明授权

US07403412B2 Integrated circuit chip with improved array stability 有权
标题翻译：集成电路芯片具有改进的阵列稳定性
公开(公告)号：US07403412B2
公开(公告)日：2008-07-22
申请号：US11782282
申请日：2007-07-24
申请人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
发明人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C8/08 , G11C11/412 , G11C11/417
摘要： A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.
摘要翻译：可以由多个电源提供的多阈值集成电路（IC），具有诸如阵列静态随机存取存储器（SRAM）单元的锁存器阵列和具有改进的稳定性和减小的亚阈值泄漏的CMOS SRAM。阵列单元中的选定器件（NFET和/或PFET）和支持逻辑，例如在数据通路和非关键逻辑中，都适用于较低的栅极和亚阈值泄漏。正常基极FET具有基极阈值，并且定制的FET具有高于阈值。在多电源芯片中，具有定制FET的电路由增加的电源电压供电。

5. 发明授权

US07873891B2 Programmable voltage divider 有权
标题翻译：可编程分压器
公开(公告)号：US07873891B2
公开(公告)日：2011-01-18
申请号：US12114853
申请日：2008-05-05
申请人： Yuen H. Chan , Rajiv V. Joshi
发明人： Yuen H. Chan , Rajiv V. Joshi
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.
摘要翻译：可以在测试电路中使用的测试电路和可编程分压器。可编程分压器产生可以数字选择的电压差信号。测试电路可用于测试和表征读出放大器。可编程分压器产生具有所选极性和幅度的信号，该极性和幅度被提供给被测试的读出放大器。读出放大器设置并输出锁存。根据预期值检查锁存内容。可以改变差值电压，重新测试路径以找到通过点和故障点。

6. 发明授权

US07170799B2 SRAM and dual single ended bit sense for an SRAM 失效
标题翻译：用于SRAM的SRAM和双单端位检测
公开(公告)号：US07170799B2
公开(公告)日：2007-01-30
申请号：US11055416
申请日：2005-02-10
申请人： Yuen H. Chan , Timothy J. Charest , Rajiv V. Joshi , Antonio Pelella
发明人： Yuen H. Chan , Timothy J. Charest , Rajiv V. Joshi , Antonio Pelella
IPC分类号： G11C7/00
CPC分类号： G11C11/417
摘要： A CMOS static random access memory (SRAM) and a bit select for the SRAM. The bit select includes a dual single-ended sense receiving a difference signal on a bit line pair and selectively sensing signals developing on each bit line independently of the other. Single ended outputs from the dual-ended sense are provided to an output driver. The output driver provides a pair of selectively-complementary output signals.
摘要翻译： CMOS静态随机存取存储器（SRAM）和SRAM的位选择。位选择包括双位单端感测，其接收位线对上的差分信号，并且选择性地感测在每个位线上独立于另一位置产生的信号。双端输出的单端输出提供给输出驱动器。输出驱动器提供一对选择性互补的输出信号。

7. 发明授权

US07447964B2 Difference signal path test and characterization circuit 失效
标题翻译：差分信号路径测试和表征电路
公开(公告)号：US07447964B2
公开(公告)日：2008-11-04
申请号：US11028174
申请日：2005-01-03
申请人： Yuen H. Chan , Rajiv V. Joshi
发明人： Yuen H. Chan , Rajiv V. Joshi
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.
摘要翻译：可以在测试电路中使用的测试电路和可编程分压器。可编程分压器产生可以数字选择的电压差信号。测试电路可用于测试和表征读出放大器。可编程分压器产生具有所选极性和幅度的信号，该极性和幅度被提供给被测试的读出放大器。读出放大器设置并输出锁存。根据预期值检查锁存内容。可以改变差值电压，重新测试路径以找到通过点和故障点。

8. 发明申请

US20080270864A1 DIFFERENCE SIGNAL PATH TEST AND CHARACTERIZATION CIRCUIT 审中-公开
标题翻译：差分信号路径测试和特征电路
公开(公告)号：US20080270864A1
公开(公告)日：2008-10-30
申请号：US12169664
申请日：2008-07-09
申请人： Yuen H. Chan , Rajiv V. Joshi
发明人： Yuen H. Chan , Rajiv V. Joshi
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.
摘要翻译：可以在测试电路中使用的测试电路和可编程分压器。可编程分压器产生可以数字选择的电压差信号。测试电路可用于测试和表征读出放大器。可编程分压器产生具有所选极性和幅度的信号，该极性和幅度被提供给被测试的读出放大器。读出放大器设置并输出锁存。根据预期值检查锁存内容。可以改变差值电压，重新测试路径以找到通过点和故障点。

9. 发明申请

US20080203980A1 PROGRAMMABLE VOLTAGE DIVIDER 有权
标题翻译：可编程电压分频器
公开(公告)号：US20080203980A1
公开(公告)日：2008-08-28
申请号：US12114853
申请日：2008-05-05
申请人： Yuen H. Chan , Rajiv V. Joshi
发明人： Yuen H. Chan , Rajiv V. Joshi
IPC分类号： G05F1/652
CPC分类号： G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.
摘要翻译：可以在测试电路中使用的测试电路和可编程分压器。可编程分压器产生可以数字选择的电压差信号。测试电路可用于测试和表征读出放大器。可编程分压器产生具有所选极性和幅度的信号，该极性和幅度被提供给被测试的读出放大器。读出放大器设置并输出锁存。根据预期值检查锁存内容。可以改变差值电压，重新测试路径以找到通过点和故障点。

10. 发明授权

US06990038B1 Clock driver and boundary latch for a multi-port SRAM 失效
标题翻译：多端口SRAM的时钟驱动器和边界锁存器
公开(公告)号：US06990038B1
公开(公告)日：2006-01-24
申请号：US11056803
申请日：2005-02-11
申请人： Yuen H. Chan , Timothy J. Charest , Rajiv V. Joshi , Rolf Sautter
发明人： Yuen H. Chan , Timothy J. Charest , Rajiv V. Joshi , Rolf Sautter
IPC分类号： G11C8/00
CPC分类号： G11C29/12015 , G11C8/16 , G11C11/41 , G11C11/417 , G11C29/32 , G11C2029/3202
摘要： A multi-port (e.g., two port) CMOS static random access memory (SRAM) with a local clock driver generating clocks for boundary latches. Local clocks select between address inputs clocked into the boundary latches. A read clock selects and latches a read address in the boundary latches. A second clock latches write addresses and, when appropriate, test data addresses.
摘要翻译：具有为边界锁存器产生时钟的本地时钟驱动器的多端口（例如，两端口）CMOS静态随机存取存储器（SRAM）。本地时钟选择时钟输入边界锁存器的地址输入。读取时钟选择并锁存边界锁存器中的读取地址。第二个时钟锁存写入地址，并在适当时锁定测试数据地址。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式