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1. 发明申请

US20120008379A1 GLOBAL BIT LINE RESTORE BY MOST SIGNIFICANT BIT OF AN ADDRESS LINE 失效
标题翻译：全球位线由地址线最重要的位复原
公开(公告)号：US20120008379A1
公开(公告)日：2012-01-12
申请号：US13179684
申请日：2011-07-11
申请人： Yuen H. CHAN , Michael KUGEL , Raphael POLIG , Tobias T. WERNER
发明人： Yuen H. CHAN , Michael KUGEL , Raphael POLIG , Tobias T. WERNER
IPC分类号： G11C11/00 , G11C7/12
CPC分类号： G11C11/419 , G11C7/12
摘要： An SRAM circuitry having SRAM cells for storing at least one data word of a length of at least one bit is provided. Each bit of the data words is stored in an assigned SRAM cell, wherein the SRAM circuitry comprises address lines for addressing the at least one data word, a decoding unit for decoding the address signals on the address lines to generate a word line signals on a word line per addressed word, a local bit line to be coupled to SRAM cells of different data words with different addresses, a global bit line to be coupled to the local bit line, and a global bit line restore unit for pre-charging the global bit line. The global bit line restore unit is configured for being triggered by a trigger signal based on the address signal of one of the decoded address lines.
摘要翻译：提供具有用于存储至少一个长度为至少一位的至少一个数据字的SRAM单元的SRAM电路。数据字的每一位被存储在分配的SRAM单元中，其中SRAM电路包括用于寻址至少一个数据字的地址线，解码单元，用于对地址线上的地址信号进行解码，以产生一个字线信号每个寻址字的字线，要耦合到具有不同地址的不同数据字的SRAM单元的局部位线，要耦合到本地位线的全局位线，以及用于对全局进行预充电的全局位线恢复单元位线。全局位线恢复单元被配置为基于解码的地址线之一的地址信号由触发信号触发。

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