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1. 发明申请

US20110304370A1 PROGRAMMABLE CONTROL CLOCK CIRCUIT INCLUDING SCAN MODE 失效
标题翻译：可编程控制时钟电路，包括扫描模式
公开(公告)号：US20110304370A1
公开(公告)日：2011-12-15
申请号：US12796970
申请日：2010-06-09
申请人： Paul A. Bunce , Yuen H. Chan , John D. Davis , Richard E. Serton
发明人： Paul A. Bunce , Yuen H. Chan , John D. Davis , Richard E. Serton
IPC分类号： H03K5/04
CPC分类号： H03K5/156
摘要： A programmable clock control circuit includes a base block configured to control operation of the programmable clock control circuit and a chop block configured to control the width of an output clock signal of the programmable clock control circuit. The circuit also includes a pulse width variation block providing a pulse width variation output to the base block, the base block output being variable to provide at least three different output pulse widths. The circuit also includes a launch clock delay block coupled to delay the output of the base block and a scan clock delay block to delay the output pulse and a selector that causes either the scan clock delay block or the launch clock delay block to be active based on a value of a scan gate signal.
摘要翻译：可编程时钟控制电路包括被配置为控制可编程时钟控制电路的操作的基本块和被配置为控制可编程时钟控制电路的输出时钟信号的宽度的斩波块。电路还包括提供脉冲宽度变化输出到基本块的脉冲宽度变化块，基本块输出是可变的以提供至少三个不同的输出脉冲宽度。电路还包括发射时钟延迟块，其耦合以延迟基本块的输出和延迟输出脉冲的扫描时钟延迟块和使得扫描时钟延迟块或启动时钟延迟块基于有源的选择器对扫描门信号的值。

2. 发明授权

US08299833B2 Programmable control clock circuit including scan mode 失效
标题翻译：可编程控制时钟电路包括扫描模式
公开(公告)号：US08299833B2
公开(公告)日：2012-10-30
申请号：US12796970
申请日：2010-06-09
申请人： Paul A. Bunce , Yuen H. Chan , John D. Davis , Richard E. Serton
发明人： Paul A. Bunce , Yuen H. Chan , John D. Davis , Richard E. Serton
IPC分类号： H03K3/017
CPC分类号： H03K5/156
摘要： A programmable clock control circuit includes a base block configured to control operation of the programmable clock control circuit and a chop block configured to control the width of an output clock signal of the programmable clock control circuit. The circuit also includes a pulse width variation block providing a pulse width variation output to the base block, the base block output being variable to provide at least three different output pulse widths. The circuit also includes a launch clock delay block coupled to delay the output of the base block and a scan clock delay block to delay the output pulse and a selector that causes either the scan clock delay block or the launch clock delay block to be active based on a value of a scan gate signal.
摘要翻译：可编程时钟控制电路包括被配置为控制可编程时钟控制电路的操作的基本块和被配置为控制可编程时钟控制电路的输出时钟信号的宽度的斩波块。电路还包括提供脉冲宽度变化输出到基本块的脉冲宽度变化块，基本块输出是可变的以提供至少三个不同的输出脉冲宽度。电路还包括发射时钟延迟块，其耦合以延迟基本块的输出和延迟输出脉冲的扫描时钟延迟块和使得扫描时钟延迟块或启动时钟延迟块基于有源的选择器对扫描门信号的值。

3. 发明授权

US08345497B2 Internal bypassing of memory array devices 有权
标题翻译：内存阵列设备的内部旁路
公开(公告)号：US08345497B2
公开(公告)日：2013-01-01
申请号：US12822058
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
IPC分类号： G11C7/00
CPC分类号： G11C16/02 , G11C7/1048 , G11C11/413 , G11C2207/002
摘要： An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the first logic controlled by a timing signal; second logic that internally bypasses the memory read path during a write operation by decoupling it from the output node, such that a logical derivative of write data written to the memory array is also coupled to the output node, the second logic also controlled by the timing signal; and wherein a transition of the output node from the first logic state to a second logic state during the write operation occurs within a time range as that of the same transition during the read operation.
摘要翻译：用于存储器阵列的输出控制电路包括在读取和写入操作之前预先充电到第一逻辑状态的锁存输出节点; 在读取操作期间将存储器单元数据从存储器读取路径耦合到输出节点的第一逻辑，由定时信号控制的第一逻辑; 第二逻辑，其在写入操作期间通过将其与输出节点分离而在内部旁路存储器读取路径，使得写入存储器阵列的写入数据的逻辑导数也耦合到输出节点，第二逻辑也由定时控制信号; 并且其中，所述输出节点在所述写入操作期间从所述第一逻辑状态到第二逻辑状态的转变在与所述读取操作期间相同转换的时间范围内发生。

4. 发明授权

US07099203B1 Circuit and method for writing a binary value to a memory cell 失效
标题翻译：将二进制值写入存储单元的电路和方法
公开(公告)号：US07099203B1
公开(公告)日：2006-08-29
申请号：US11057281
申请日：2005-02-11
申请人： Paul A. Bunce , John D. Davis , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Donald W. Plass
IPC分类号： G11C7/10 , G11C11/00
CPC分类号： G11C7/22 , G11C2207/2263
摘要： A circuit and a method for writing a binary value to a memory cell are provided. The circuit includes a first field-effect transistor having a first drain, a first drain, and a first gate operably coupled between the first drain and the first source. The first drain is operably coupled to a first memory cell. The first gate configured to receive a first data signal. The circuit further includes a second field-effect transistor having a second drain, a second source, and a second gate operably coupled between the second drain and the second source. The drain source is operably coupled to the first memory cell. The second gate is configured to receive a second data signal. The circuit further includes a first signal inverter having a first input terminal and a first output terminal. The first output terminal is operably coupled to both of the first and second sources. The first signal inverter is configured to output a first control signal on the first output terminal when the first input terminal receives a second control signal. When the first control signal has a second logic level and the first data signal has a first logic level and the second data signal has the second logic level, the first and second field-effect transistors induce the first memory cell to store a first binary value.
摘要翻译：提供了一种将二进制值写入存储单元的电路和方法。电路包括具有第一漏极，第一漏极和第一栅极的第一场效应晶体管，其可操作地耦合在第一漏极和第一源极之间。第一漏极可操作地耦合到第一存储器单元。第一门被配置为接收第一数据信号。电路还包括第二场效应晶体管，其具有可操作地耦合在第二漏极和第二源之间的第二漏极，第二源极和第二栅极。漏源可操作地耦合到第一存储单元。第二门被配置为接收第二数据信号。电路还包括具有第一输入端和第一输出端的第一信号反相器。第一输出端子可操作地耦合到第一和第二源两者。第一信号反相器被配置为当第一输入端子接收到第二控制信号时，在第一输出端子上输出第一控制信号。当第一控制信号具有第二逻辑电平且第一数据信号具有第一逻辑电平且第二数据信号具有第二逻辑电平时，第一和第二场效应晶体管感应第一存储器单元以存储第一二进制值。

5. 发明授权

US08351278B2 Jam latch for latching memory array output data 失效
标题翻译：用于锁存存储器阵列输出数据的卡锁
公开(公告)号：US08351278B2
公开(公告)日：2013-01-08
申请号：US12822038
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/413
摘要： A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation device that selectively decouples the feedback inverter from a power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the power supply rail coincides with resetting the data node to the first logic state; and a margin test device that selectively increases pull down strength of the feedback inverter.
摘要翻译：用于数据节点的卡锁装置包括：前馈反相器，其具有耦合到数据节点的输入; 反馈逆变器，其具有连接到所述前馈逆变器的输出的输入端，所述反馈反相器的输出连接到所述数据节点; 隔离装置，其将反馈反相器与电源轨选择性地分离，该隔离装置由复位装置的时钟信号控制，该复位装置将数据节点复位到第一逻辑状态，使得反馈反相器与电源轨的解耦一致将数据节点重置为第一逻辑状态; 以及选择性地增加反馈逆变器的下拉强度的余量测试装置。

6. 发明申请

US20080247245A1 WRITE CONTROL METHOD FOR A MEMORY ARRAY CONFIGURED WITH MULTIPLE MEMORY SUBARRAYS 失效
标题翻译：用于配置多个存储器子选项的存储器阵列的写控制方法
公开(公告)号：US20080247245A1
公开(公告)日：2008-10-09
申请号：US12139675
申请日：2008-06-16
申请人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
发明人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G11C7/22
CPC分类号： G11C11/413 , G11C7/18
摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.
摘要翻译：为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。

7. 发明授权

US07233542B2 Method and apparatus for address generation 有权
标题翻译：用于地址生成的方法和装置
公开(公告)号：US07233542B2
公开(公告)日：2007-06-19
申请号：US11056048
申请日：2005-02-11
申请人： Paul A. Bunce , John D. Davis , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Donald W. Plass
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/16
摘要： A system for generating one or more common address signals for multi-port memory arrays. The system includes circuitry receiving one or more read address signal; circuitry receiving one or more write address signal; circuitry receiving an array clock signal; circuitry receiving one or more enable signal; and circuitry generating the common address signals in response to the enable signal, the array clock signal and one of the read address signal and write address signal.
摘要翻译：一种用于为多端口存储器阵列产生一个或多个公共地址信号的系统。该系统包括接收一个或多个读取地址信号的电路; 接收一个或多个写入地址信号的电路; 接收阵列时钟信号的电路; 接收一个或多个使能信号的电路; 以及响应于使能信号，阵列时钟信号和读地址信号和写入地址信号之一产生公共地址信号的电路。

8. 发明授权

US07210084B2 Integrated system logic and ABIST data compression for an SRAM directory 失效
标题翻译：用于SRAM目录的集成系统逻辑和ABIST数据压缩
公开(公告)号：US07210084B2
公开(公告)日：2007-04-24
申请号：US10413612
申请日：2003-04-14
申请人： Paul A. Bunce , John D. Davis , Thomas J. Knips , Donald Plass
发明人： Paul A. Bunce , John D. Davis , Thomas J. Knips , Donald Plass
IPC分类号： G11C29/30 , G11C29/24
CPC分类号： G11C29/40 , G11C11/41
摘要： ABIST apparatus with integrated directory compare logic functionality, and ABIST error detection functionality. The apparatus includes two subsystems NOR'ed together. The first subsystem is for bit-wise logically ANDing corresponding array valid bits and tag valid inputs, generating “0” for a match and “1” for a mis-match, and logically ORing the bit-wise result to generate a “1” hit if there are any bit-wise mismatches. The second subsystem further receives ABIST control logic as an input to either: (a). combine array valid bits tag valid inputs to produce valid output, or (b) compare array valid bits with tag valid inputs. The apparatus further includes logical NOR functionality for the outputs of the first and second subsystems.
摘要翻译：具有集成目录比较逻辑功能的ABIST设备和ABIST错误检测功能。该装置包括NORs在一起的两个子系统。第一个子系统用于逐位逻辑地对应阵列有效位和标签有效输入，为匹配产生“0”，为了匹配而产生“1”，逻辑上对位逐次结果产生“1” 如果有任何比特错配，则打。第二子系统进一步接收ABIST控制逻辑作为输入：（a）。组合数组有效位标签有效输入以产生有效输出，或（b）将数组有效位与标签有效输入进行比较。该装置还包括用于第一和第二子系统的输出的逻辑NOR功能。

9. 发明授权

US07102944B1 Programmable analog control of a bitline evaluation circuit 失效
公开(公告)号：US07102944B1
公开(公告)日：2006-09-05
申请号：US11056049
申请日：2005-02-11
申请人： Paul A. Bunce , John D. Davis , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Donald W. Plass
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/12 , G11C11/419
摘要： The invention may comprise circuit for programmable control of a discharge deactivation signal when interfacing local bitlines to a global bitline or other circuit. The invention may also comprise a method for programmable ground circuit control for control of a discharge signal deactivation when interfacing local bitlines to a global bitline via a bitline evaluation discharge device comprising: providing input logic states to inputs of a controller circuit; outputting an adjustable ground value from the controller circuit; and controlling the bitline evaluation discharge device with the adjustable ground value.

10. 发明授权

US08599642B2 Port enable signal generation for gating a memory array device output 有权
标题翻译：用于门控存储器阵列器件输出的端口使能信号生成
公开(公告)号：US08599642B2
公开(公告)日：2013-12-03
申请号：US12822021
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
IPC分类号： G11C8/18 , G06F1/04
CPC分类号： G06F1/10 , G11C11/419
摘要： A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.
摘要翻译：产生用于将存储器阵列数据门控到输出节点的动态端口使能信号的方法包括产生输入动态时钟信号的可编程前沿时钟信号导出; 产生所述输入动态时钟信号的可编程后沿时钟信号导出，其中所述前沿时钟信号导出和所述后沿时钟信号导出可相对于彼此独立地可编程; 以及利用静态输入使能信号选通产生的可编程前导和后沿时钟信号导出，以便产生端口使能信号，使得当非活动时，端口使能信号防止早期存储器阵列数据耦合到输出节点。

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