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1. 发明授权

US07098102B2 Shallow trench isolation structure and dynamic random access memory, and fabricating methods thereof 有权
标题翻译：浅沟槽隔离结构和动态随机存取存储器及其制造方法
公开(公告)号：US07098102B2
公开(公告)日：2006-08-29
申请号：US10605402
申请日：2003-09-29
申请人： Yueh-Chuan Lee , Jason Chen
发明人： Yueh-Chuan Lee , Jason Chen
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L27/1087 , H01L21/76237 , H01L27/10829 , H01L27/10867
摘要： A method for fabricating a shallow trench isolation (STI) structure is described. A patterned mask layer is formed on a substrate. An ion implantation is performed to form a doped region in a predetermined depth in the substrate exposed by the mask layer. An etching process is conducted to etch the substrate down to the doped region to form a shallow trench. Thereafter, an isolating material is filled into the shallow trench to form an STI layer. The doped region is located directly under the STI layer, and no doped region is formed in the sidewall of the shallow trench.
摘要翻译：描述了制造浅沟槽隔离（STI）结构的方法。在基板上形成图案化掩模层。进行离子注入以在由掩模层暴露的衬底中形成预定深度的掺杂区域。进行蚀刻工艺以将衬底蚀刻到掺杂区域以形成浅沟槽。此后，将隔离材料填充到浅沟槽中以形成STI层。掺杂区域位于STI层的正下方，在浅沟槽的侧壁中不形成掺杂区域。

2. 发明授权

US07034354B2 Semiconductor structure with lining layer partially etched on sidewall of the gate 有权
标题翻译：具有在栅极侧壁部分蚀刻的衬层的半导体结构
公开(公告)号：US07034354B2
公开(公告)日：2006-04-25
申请号：US10695739
申请日：2003-10-30
申请人： Yueh-Chuan Lee , Ming-Sheng Tung
发明人： Yueh-Chuan Lee , Ming-Sheng Tung
IPC分类号： H01L21/108
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28061 , H01L21/28114 , H01L21/823425 , H01L21/823456 , H01L29/42376
摘要： A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.
摘要翻译：具有部分蚀刻栅极的半导体结构及其制造方法。具有单面或双面部分蚀刻栅极的半导体结构包括依次层叠在衬底上以形成栅极结构的栅介质层，栅极导电层和覆盖层，以及设置在栅极侧壁上的衬层结构，其中衬里层被部分蚀刻以暴露相邻的栅极结构。此外，层间电介质层覆盖栅极结构，并且在层间电介质层中形成接触，将衬底和栅极结构的一部分暴露于其中，其中栅极结构的暴露部分的衬层被部分删除。

3. 发明申请

US20050127453A1 Method of forming self-aligned contact structure with locally etched gate conductive layer 审中-公开
标题翻译：用局部蚀刻的栅极导电层形成自对准接触结构的方法
公开(公告)号：US20050127453A1
公开(公告)日：2005-06-16
申请号：US11041503
申请日：2005-01-21
申请人： Ming-Sheng Tung , Yueh-Chuan Lee
发明人： Ming-Sheng Tung , Yueh-Chuan Lee
IPC分类号： H01L21/336 , H01L21/60 , H01L23/485 , H01L21/8242 , H01L31/062 , H01L31/113
CPC分类号： H01L21/76897 , H01L23/485 , H01L29/66659 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a self-aligned contact structure with a locally etched conductive layer comprises the steps of: preparing a substrate formed with gate structures comprising a first conductive layer, a second conductive layer, and an insulating layer; depositing a photoresist material layer on the substrate; performing a lithographic step with a bit-line contact node photomask or a bit-line contact photomask to expose a portion of the surface of the substrate; etching the exposed second conductive layer with an etchant; removing the remaining photoresist material layer; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer to cover the substrate; and performing lithographic and etching steps to remove the dielectric layer and to form self-aligned contact structure.
摘要翻译：用局部蚀刻的导电层形成自对准接触结构的方法包括以下步骤：制备由栅极结构形成的衬底，该栅极结构包括第一导电层，第二导电层和绝缘层; 在基板上沉积光致抗蚀剂材料层; 用位线接触节点光掩模或位线接触光掩模执行光刻步骤以暴露所述衬底表面的一部分; 用蚀刻剂蚀刻暴露的第二导电层; 去除剩余的光致抗蚀剂材料层; 在每个栅极结构的侧壁上形成侧壁间隔物; 形成介电层以覆盖基板; 并执行光刻和蚀刻步骤以去除介电层并形成自对准接触结构。

4. 发明申请

US20050106844A1 Method of fabricating a MOSFET device 审中-公开
标题翻译：制造MOSFET器件的方法
公开(公告)号：US20050106844A1
公开(公告)日：2005-05-19
申请号：US10788807
申请日：2004-02-27
申请人： Ming-Sheng Tung , Yueh-Chuan Lee , Fang-Yu Yeh , Chi Lin
发明人： Ming-Sheng Tung , Yueh-Chuan Lee , Fang-Yu Yeh , Chi Lin
IPC分类号： H01L21/336 , H01L29/10
CPC分类号： H01L29/6653 , H01L29/1045 , H01L29/6659 , H01L29/66659
摘要： Ions are implanted into a substrate, using a gate and its sidewall liner on the substrate as the mask, to form a source/drain region in the substrate beneath the liner and adjacent to the two sides of the gate. The liner is etched to reduce its thickness. Then, ions are implanted into the substrate to form a halo doped region surrounding the source/drain region. The halo doped region is closer to the MOSFET channel region and overlaps less with the source/drain region. Therefore, the device threshold voltage can be sustained and the junction leakage can also be minimized.
摘要翻译：将离子以植入基板上的栅极及其侧壁衬垫作为掩模注入到衬底中，以在衬底下面形成源极/漏极区域，并且邻近栅极的两侧。蚀刻衬里以减小其厚度。然后，将离子注入到衬底中以形成围绕源/漏区的卤素掺杂区。卤素掺杂区域更靠近MOSFET沟道区域，并且与源极/漏极区域重叠较小。因此，可以维持器件阈值电压，也可以最小化结漏电。

5. 发明申请

US20050079681A1 Deep-trench capacitor with hemispherical grain silicon surface and method for making the same 有权
标题翻译：具有半球形硅表面的深沟槽电容器及其制造方法
公开(公告)号：US20050079681A1
公开(公告)日：2005-04-14
申请号：US10967181
申请日：2004-10-19
申请人： Yueh-Chuan Lee , Shih-Lung Chen
发明人： Yueh-Chuan Lee , Shih-Lung Chen
IPC分类号： H01L21/334 , H01L21/8242 , H01L29/94 , H01L21/20
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945 , Y10S438/923
摘要： A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.
摘要翻译：一种制造沟槽电容器的方法，包括提供半导体衬底，在衬底中形成深沟槽，在沟槽的表面上形成薄的牺牲层，以及在薄牺牲层上形成半球状硅晶粒层，其中牺牲层层的厚度在随后的步骤中用作蚀刻停止以去除半球状硅晶粒层的至少一部分，并且是导电的。

6. 发明授权

US06855610B2 Method of forming self-aligned contact structure with locally etched gate conductive layer 有权
标题翻译：用局部蚀刻的栅极导电层形成自对准接触结构的方法
公开(公告)号：US06855610B2
公开(公告)日：2005-02-15
申请号：US10330522
申请日：2002-12-27
申请人： Ming-Sheng Tung , Yueh-Chuan Lee
发明人： Ming-Sheng Tung , Yueh-Chuan Lee
IPC分类号： H01L21/336 , H01L21/60 , H01L23/485
CPC分类号： H01L21/76897 , H01L23/485 , H01L29/66659 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a self-aligned contact structure with a locally etched conductive layer comprises the steps of: preparing a substrate formed with gate structures comprising a first conductive layer, a second conductive layer, and an insulating layer; depositing a photoresist material layer on the substrate; performing a lithographic step with a bit-line contact node photomask or a bit-line contact photomask to expose a portion of the surface of the substrate; etching the exposed second conductive layer with an etchant; removing the remaining photoresist material layer; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer to cover the substrate; and performing lithographic and etching steps to remove the dielectric layer and to form self-aligned contact structure.
摘要翻译：用局部蚀刻的导电层形成自对准接触结构的方法包括以下步骤：制备由栅极结构形成的衬底，该栅极结构包括第一导电层，第二导电层和绝缘层; 在基板上沉积光致抗蚀剂材料层; 用位线接触节点光掩模或位线接触光掩模执行光刻步骤以暴露所述衬底表面的一部分; 用蚀刻剂蚀刻暴露的第二导电层; 去除剩余的光致抗蚀剂材料层; 在每个栅极结构的侧壁上形成侧壁间隔物; 形成介电层以覆盖基板; 并执行光刻和蚀刻步骤以去除介电层并形成自对准接触结构。

7. 发明授权

US06251753B1 Method of sidewall capping for degradation-free damascene trenches of low dielectric constant dielectric by selective liquid-phase deposition 有权
标题翻译：通过选择性液相沉积对低介电常数电介质的无降解镶嵌沟槽进行侧壁封盖的方法
公开(公告)号：US06251753B1
公开(公告)日：2001-06-26
申请号：US09447715
申请日：1999-11-23
申请人： Ching-Fa Yeh , Yueh-Chuan Lee , Yuh-Ching Su , Kwo-Hau Wu
发明人： Ching-Fa Yeh , Yueh-Chuan Lee , Yuh-Ching Su , Kwo-Hau Wu
IPC分类号： H01L2176
CPC分类号： H01L21/02137 , H01L21/02282 , H01L21/02362 , H01L21/3122 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76831
摘要： A low dielectric constant (k) material, such as methylsilsesquioxane (MSQ), used as an interlevel dielectric is expected to reduce the parasitic capacitance in integrated circuit. However, MSQ film can be easily degraded during resist ashing after the film is etched with the damascene trenches being created. The present invention discloses an innovative sidewall capping technology to solve the degradation issue. Prior to resist ashing, a high-quality, low-k oxide film is selectively deposited onto the sidewalls of MSQ trenches using selective liquid-phase deposition. Experimental results demonstrate that the capping oxide can effectively protect the sidewalls of MSQ trenches from ashing-induced degradation.
摘要翻译：用作层间电介质的低介电常数（k）材料，如甲基倍半硅氧烷（MSQ），有望降低集成电路中的寄生电容。然而，在蚀刻形成镶嵌的沟槽之后的抗蚀剂灰化过程中，MSQ膜可以容易地劣化。本发明公开了一种创新的侧壁封盖技术来解决退化问题。在抗蚀灰化之前，使用选择性液相沉积将高质量，低k氧化物膜选择性地沉积在MSQ沟槽的侧壁上。实验结果表明，覆盖氧化物可以有效地保护MSQ沟槽的侧壁免受灰分诱导的退化。

8. 发明申请

US20090008781A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090008781A1
公开(公告)日：2009-01-08
申请号：US12211068
申请日：2008-09-15
申请人： Bai-rou Ni , Fang-Yu Yeh , Yueh-Chuan Lee
发明人： Bai-rou Ni , Fang-Yu Yeh , Yueh-Chuan Lee
IPC分类号： H01L29/51
CPC分类号： H01L21/28061 , H01L21/823443 , H01L21/82345 , H01L21/823835 , H01L21/823842 , H01L29/51 , H01L29/66583
摘要： A semiconductor device structure includes a substrate, a first conductive layer over the substrate, a second conductive layer between the first conductive layer and the substrate and extending over the sidewalls of the first conductive layer, a dielectric layer between the second conductive layer and the substrate, a cap layer over the first conductive layer and the second conductive layer, and a liner layer on the sidewalls of the second conductive layer.
摘要翻译：半导体器件结构包括衬底，在衬底上的第一导电层，在第一导电层和衬底之间并在第一导电层的侧壁上延伸的第二导电层，在第二导电层和衬底之间的介电层，在第一导电层和第二导电层之上的覆盖层，以及在第二导电层的侧壁上的衬层。

9. 发明授权

US07241659B2 Volatile memory devices and methods for forming same 失效
标题翻译：易失性存储器件及其形成方法
公开(公告)号：US07241659B2
公开(公告)日：2007-07-10
申请号：US10983664
申请日：2004-11-09
申请人： Chin-Long Hung , Hong-Long Chang , Yueh-Chuan Lee
发明人： Chin-Long Hung , Hong-Long Chang , Yueh-Chuan Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867
摘要： A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low level portion and a high level portion adjacent to a predetermined active area of the volatile memory device.
摘要翻译：一种用于形成易失性存储器件的方法。提供了包括一对相邻沟槽的衬底，每个沟槽包括电容器。在每个沟槽的上侧壁上形成轴环绝缘层。轴环绝缘层包括与易失性存储装置的预定有效区域相邻的低电平部分和高电平部分。

10. 发明授权

US07009238B2 Deep-trench capacitor with hemispherical grain silicon surface and method for making the same 有权
标题翻译：具有半球形硅表面的深沟槽电容器及其制造方法
公开(公告)号：US07009238B2
公开(公告)日：2006-03-07
申请号：US10967181
申请日：2004-10-19
申请人： Yueh-Chuan Lee , Shih-Lung Chen
发明人： Yueh-Chuan Lee , Shih-Lung Chen
IPC分类号： H01L29/76
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945 , Y10S438/923
摘要： A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.
摘要翻译：一种制造沟槽电容器的方法，包括提供半导体衬底，在衬底中形成深沟槽，在沟槽的表面上形成薄的牺牲层，以及在薄牺牲层上形成半球状硅晶粒层，其中牺牲层层的厚度在随后的步骤中用作蚀刻停止以去除半球状硅晶粒层的至少一部分，并且是导电的。

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