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1. 发明申请

US20080096346A1 Method for Preparing a Trench Capacitor Structure 失效
标题翻译：制备沟槽电容器结构的方法
公开(公告)号：US20080096346A1
公开(公告)日：2008-04-24
申请号：US11561957
申请日：2006-11-21
申请人： Ching Lee , Chin Wen Lee , Chin Long Hung , Zheng Cheng Chen
发明人： Ching Lee , Chin Wen Lee , Chin Long Hung , Zheng Cheng Chen
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L29/66181
摘要： A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a first dielectric layer covering an inner surface of the bottom electrode and a top electrode positioned on the surface of the dielectric layer. Subsequently, a collar insulation layer is formed on the surface of the first dielectric layer above the top electrode, and a first conductive block is then formed in the collar insulation layer. A second conductive block with dopants is formed on the first conductive block, and a thermal treating process is performed to diffuse the dopants from the second conductive block into an upper portion of the semiconductor substrate to form a buried conductive region.
摘要翻译：制备沟槽电容器结构的方法首先在衬底中形成至少一个沟槽，并且在沟槽的底部形成电容器结构，其中电容器结构包括位于沟槽的下外表面上的掩埋底电极，覆盖所述底部电极的内表面的第一电介质层和位于所述电介质层的表面上的顶部电极。随后，在顶部电极上方的第一介电层的表面上形成轴环绝缘层，然后在轴环绝缘层中形成第一导电块。具有掺杂剂的第二导电块形成在第一导电块上，并且执行热处理工艺以将掺杂剂从第二导电块扩散到半导体衬底的上部以形成掩埋导电区域。

2. 发明授权

US07241659B2 Volatile memory devices and methods for forming same 失效
标题翻译：易失性存储器件及其形成方法
公开(公告)号：US07241659B2
公开(公告)日：2007-07-10
申请号：US10983664
申请日：2004-11-09
申请人： Chin-Long Hung , Hong-Long Chang , Yueh-Chuan Lee
发明人： Chin-Long Hung , Hong-Long Chang , Yueh-Chuan Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867
摘要： A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low level portion and a high level portion adjacent to a predetermined active area of the volatile memory device.
摘要翻译：一种用于形成易失性存储器件的方法。提供了包括一对相邻沟槽的衬底，每个沟槽包括电容器。在每个沟槽的上侧壁上形成轴环绝缘层。轴环绝缘层包括与易失性存储装置的预定有效区域相邻的低电平部分和高电平部分。

3. 发明申请

US20050067648A1 Volatile memory devices and methods for forming same 失效
标题翻译：易失性存储器件及其形成方法
公开(公告)号：US20050067648A1
公开(公告)日：2005-03-31
申请号：US10983664
申请日：2004-11-09
申请人： Chin-Long Hung , Hong-Long Chang , Yueh-Chuan Lee
发明人： Chin-Long Hung , Hong-Long Chang , Yueh-Chuan Lee
IPC分类号： H01L21/8242 , H01L21/8244 , H01L29/76
CPC分类号： H01L27/10867
摘要： A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low level portion and a high level portion adjacent to a predetermined active area of the volatile memory device.
摘要翻译：一种用于形成易失性存储器件的方法。提供了包括一对相邻沟槽的衬底，每个沟槽包括电容器。在每个沟槽的上侧壁上形成轴环绝缘层。轴环绝缘层包括与易失性存储装置的预定有效区域相邻的低电平部分和高电平部分。

4. 发明授权

US07419872B2 Method for preparing a trench capacitor structure 失效
标题翻译：制备沟槽电容器结构的方法
公开(公告)号：US07419872B2
公开(公告)日：2008-09-02
申请号：US11561957
申请日：2006-11-21
申请人： Ching Lee , Chin Wen Lee , Chin Long Hung , Zheng Cheng Chen
发明人： Ching Lee , Chin Wen Lee , Chin Long Hung , Zheng Cheng Chen
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181
摘要： A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a first dielectric layer covering an inner surface of the bottom electrode and a top electrode positioned on the surface of the dielectric layer. Subsequently, a collar insulation layer is formed on the surface of the first dielectric layer above the top electrode, and a first conductive block is then formed in the collar insulation layer. A second conductive block with dopants is formed on the first conductive block, and a thermal treating process is performed to diffuse the dopants from the second conductive block into an upper portion of the semiconductor substrate to form a buried conductive region.
摘要翻译：制备沟槽电容器结构的方法首先在衬底中形成至少一个沟槽，并且在沟槽的底部形成电容器结构，其中电容器结构包括位于沟槽的下外表面上的掩埋底电极，覆盖所述底部电极的内表面的第一电介质层和位于所述电介质层的表面上的顶部电极。随后，在顶部电极上方的第一介电层的表面上形成轴环绝缘层，然后在轴环绝缘层中形成第一导电块。具有掺杂剂的第二导电块形成在第一导电块上，并且执行热处理工艺以将掺杂剂从第二导电块扩散到半导体衬底的上部以形成掩埋导电区域。

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