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1. 发明授权

US06294832B1 Semiconductor device having structure of copper interconnect/barrier dielectric liner/low-k dielectric trench and its fabrication method 有权
标题翻译：具有铜互连/阻挡电介质衬垫/低k电介质沟槽结构的半导体器件及其制造方法
公开(公告)号：US06294832B1
公开(公告)日：2001-09-25
申请号：US09546539
申请日：2000-04-10
申请人： Ching-Fa Yeh , Yueh-Chuan Lee , Kwo-Hau Wu , Yuh-Ching Su
发明人： Ching-Fa Yeh , Yueh-Chuan Lee , Kwo-Hau Wu , Yuh-Ching Su
IPC分类号： H01L2348
CPC分类号： H01L21/02131 , H01L21/0214 , H01L21/02282 , H01L21/02321 , H01L21/0234 , H01L21/3122 , H01L21/3124 , H01L21/31629 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L21/76835 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present invention is related to a interconnection structure with Cu interconnects and low-k dielectric, in which a barrier dielectric liner made of a nitrogen-containing liquid-phase-deposition (LPD) fluorosilicate glass (FSG) film is used to replace a barrier metal layer and an oxide liner.
摘要翻译：本发明涉及具有Cu互连和低k电介质的互连结构，其中使用由含氮液相沉积（LPD）氟硅酸盐玻璃（FSG）膜制成的阻挡介电衬垫来代替阻挡层金属层和氧化物衬垫。

2. 发明授权

US06251753B1 Method of sidewall capping for degradation-free damascene trenches of low dielectric constant dielectric by selective liquid-phase deposition 有权
标题翻译：通过选择性液相沉积对低介电常数电介质的无降解镶嵌沟槽进行侧壁封盖的方法
公开(公告)号：US06251753B1
公开(公告)日：2001-06-26
申请号：US09447715
申请日：1999-11-23
申请人： Ching-Fa Yeh , Yueh-Chuan Lee , Yuh-Ching Su , Kwo-Hau Wu
发明人： Ching-Fa Yeh , Yueh-Chuan Lee , Yuh-Ching Su , Kwo-Hau Wu
IPC分类号： H01L2176
CPC分类号： H01L21/02137 , H01L21/02282 , H01L21/02362 , H01L21/3122 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76831
摘要： A low dielectric constant (k) material, such as methylsilsesquioxane (MSQ), used as an interlevel dielectric is expected to reduce the parasitic capacitance in integrated circuit. However, MSQ film can be easily degraded during resist ashing after the film is etched with the damascene trenches being created. The present invention discloses an innovative sidewall capping technology to solve the degradation issue. Prior to resist ashing, a high-quality, low-k oxide film is selectively deposited onto the sidewalls of MSQ trenches using selective liquid-phase deposition. Experimental results demonstrate that the capping oxide can effectively protect the sidewalls of MSQ trenches from ashing-induced degradation.
摘要翻译：用作层间电介质的低介电常数（k）材料，如甲基倍半硅氧烷（MSQ），有望降低集成电路中的寄生电容。然而，在蚀刻形成镶嵌的沟槽之后的抗蚀剂灰化过程中，MSQ膜可以容易地劣化。本发明公开了一种创新的侧壁封盖技术来解决退化问题。在抗蚀灰化之前，使用选择性液相沉积将高质量，低k氧化物膜选择性地沉积在MSQ沟槽的侧壁上。实验结果表明，覆盖氧化物可以有效地保护MSQ沟槽的侧壁免受灰分诱导的退化。

3. 发明授权

US06903029B2 Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure 失效
标题翻译：降低旋涂电介质厚膜应力的方法和所得夹心电介质结构
公开(公告)号：US06903029B2
公开(公告)日：2005-06-07
申请号：US10893263
申请日：2004-07-19
申请人： Ching-Fa Yeh , Yueh-Chuan Lee , Chih-Chuan Hsu , Kwo-Hau Wu , Shuo-Cheng Wang
发明人： Ching-Fa Yeh , Yueh-Chuan Lee , Chih-Chuan Hsu , Kwo-Hau Wu , Shuo-Cheng Wang
IPC分类号： H01L21/312 , H01L21/316 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76801 , H01L21/02131 , H01L21/02137 , H01L21/022 , H01L21/02282 , H01L21/02332 , H01L21/0234 , H01L21/3122 , H01L21/316 , H01L21/31629 , H01L21/76826 , H01L21/76828 , H01L21/76829 , Y10T428/265
摘要： The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.
摘要翻译：本发明提供一种通过形成夹层电介质结构来减小厚的自旋电介质层的应力的技术，其中通过旋涂形成在基板上的第一介电层，形成液相沉积（LPD）二氧化硅层第一电介质层，并且通过旋涂在LPD二氧化硅层上形成第二电介质层。可以进一步对LPD二氧化硅层进行氮等离子体处理，以提高其热稳定性和抗水渗透能力。

4. 发明授权

US06774461B2 Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure 有权
标题翻译：降低旋涂电介质厚膜应力的方法和所得夹心电介质结构
公开(公告)号：US06774461B2
公开(公告)日：2004-08-10
申请号：US10075293
申请日：2002-02-15
申请人： Ching-Fa Yeh , Yueh-Chuan Lee , Chih-Chuan Hsu , Kwo-Hau Wu , Shuo-Cheng Wang
发明人： Ching-Fa Yeh , Yueh-Chuan Lee , Chih-Chuan Hsu , Kwo-Hau Wu , Shuo-Cheng Wang
IPC分类号： H01L2358
CPC分类号： H01L21/76801 , H01L21/02131 , H01L21/02137 , H01L21/022 , H01L21/02282 , H01L21/02332 , H01L21/0234 , H01L21/3122 , H01L21/316 , H01L21/31629 , H01L21/76826 , H01L21/76828 , H01L21/76829 , Y10T428/265
摘要： The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.
摘要翻译：本发明提供一种通过形成夹层电介质结构来减小厚的自旋电介质层的应力的技术，其中通过旋涂形成在基板上的第一介电层，形成液相沉积（LPD）二氧化硅层第一电介质层，并且通过旋涂在LPD二氧化硅层上形成第二电介质层。可以进一步对LPD二氧化硅层进行氮等离子体处理，以提高其热稳定性和抗水渗透能力。

5. 发明授权

US06486057B1 Process for preparing Cu damascene interconnection 有权
标题翻译：制备Cu镶嵌互连的工艺
公开(公告)号：US06486057B1
公开(公告)日：2002-11-26
申请号：US10107146
申请日：2002-03-28
申请人： Ching-Fa Yeh , Yueh-Chuan Lee , Chien-Hsing Lin
发明人： Ching-Fa Yeh , Yueh-Chuan Lee , Chien-Hsing Lin
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/76826 , H01L21/76834
摘要： The present invention discloses a technique of enhancing adhesion between a passivation layer and a low-K dielectric layer, in which a SiO2 layer as the passivation formed on the low-K dielectric layer is subjected to N2O plasma annealing. This technique is useful in improving the yield of a process for preparing Cu damascene interconnection.
摘要翻译：本发明公开了一种增强钝化层和低K电介质层之间的粘附性的技术，其中在低K电介质层上形成的钝化层的SiO2层进行N2O等离子体退火。该技术可用于提高制备Cu镶嵌互连的方法的产率。

6. 发明申请

US20060128157A1 Semiconductor structure with partially etched gate and method of fabricating the same 审中-公开
标题翻译：具有部分蚀刻栅极的半导体结构及其制造方法
公开(公告)号：US20060128157A1
公开(公告)日：2006-06-15
申请号：US11338679
申请日：2006-01-25
申请人： Yueh-Chuan Lee , Ming-Sheng Tung
发明人： Yueh-Chuan Lee , Ming-Sheng Tung
IPC分类号： H01L21/311 , H01L21/461 , H01L21/302
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28061 , H01L21/28114 , H01L21/823425 , H01L21/823456 , H01L29/42376
摘要： A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.
摘要翻译：具有部分蚀刻栅极的半导体结构及其制造方法。具有单面或双面部分蚀刻栅极的半导体结构包括依次层叠在衬底上以形成栅极结构的栅介质层，栅极导电层和覆盖层，以及设置在栅极侧壁上的衬层结构，其中衬里层被部分蚀刻以暴露相邻的栅极结构。此外，层间电介质层覆盖栅极结构，并且在层间电介质层中形成接触，将衬底和栅极结构的一部分暴露于其中，其中栅极结构的暴露部分的衬层被部分删除。

7. 发明授权

US06821842B1 [DRAM structure and fabricating method thereof] 有权
标题翻译： [DRAM结构及其制造方法]
公开(公告)号：US06821842B1
公开(公告)日：2004-11-23
申请号：US10708227
申请日：2004-02-18
申请人： Yueh-Chuan Lee , Shih-Lung Chen
发明人： Yueh-Chuan Lee , Shih-Lung Chen
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/10873 , H01L29/66181 , H01L29/945
摘要： A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure. The doped region is formed in a self-aligned process by conducting a tilt implantation implanting ions into the substrate through the upper portion of the capacitor trench adjacent to the channel region after forming the trench but before the definition of the active region.
摘要翻译：提供了一种动态随机存取存储器（DRAM）结构及其制造方法。在制造过程中，在与隔离结构相邻的部分中，沟道区域形成有与衬底相同的导电性的掺杂区域。通过在形成沟槽之后但在有源区的定义之前，通过在邻近沟道区的电容器沟槽的上部通过进行倾斜注入而将离子注入到衬底中来形成掺杂区。

8. 发明授权

US06680237B2 Method of manufacturing deep trench capacitor 有权
标题翻译：制造深沟槽电容器的方法
公开(公告)号：US06680237B2
公开(公告)日：2004-01-20
申请号：US09967709
申请日：2001-09-27
申请人： Shih-Lung Chen , Hsiao-Lei Wang , Hwei-Lin Chuang , Yueh-Chuan Lee
发明人： Shih-Lung Chen , Hsiao-Lei Wang , Hwei-Lin Chuang , Yueh-Chuan Lee
IPC分类号： H01L2120
CPC分类号： H01L27/10867
摘要： A method of manufacturing a deep trench capacitor. A deep trench is formed in a substrate. A conformal capacitor dielectric layer and a first conductive layer are sequentially formed, completely filling the deep trench. The first conductive layer has a seam. The first conductive layer is etched to open up the seam. A collar oxide layer is formed over the interior surface of the deep trench. A collar liner layer is formed over the collar oxide layer inside the deep trench. Using the collar liner layer as a mask, the collar oxide material above the first conductive layer and within the seam is removed. The collar liner layer is removed. Finally, a second conductive layer and a third conductive layer are sequentially formed inside the deep trench.
摘要翻译：一种制造深沟槽电容器的方法。在衬底中形成深沟槽。依次形成保形电容器电介质层和第一导电层，完全填充深沟槽。第一导电层具有接缝。蚀刻第一导电层以打开接缝。在深沟槽的内表面上形成环状氧化物层。在深沟槽内部的轴环氧化物层上方形成轴环衬层。使用套环内层作为掩模，去除第一导电层上方和接缝内的环氧化物材料。衣领衬里层被去除。最后，在深沟槽内依次形成第二导电层和第三导电层。

9. 发明授权

US07320912B2 Trench capacitors with buried isolation layer formed by an oxidation process and methods for manufacturing the same 有权
标题翻译：通过氧化工艺形成的具有掩埋隔离层的沟槽电容器及其制造方法
公开(公告)号：US07320912B2
公开(公告)日：2008-01-22
申请号：US11125676
申请日：2005-05-10
申请人： Yueh-Chuan Lee , Ming-Sheng Tung
发明人： Yueh-Chuan Lee , Ming-Sheng Tung
IPC分类号： H01L21/8242
CPC分类号： H01L29/945 , H01L27/1087
摘要： A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in areas surrounding a lower portion of the trench; forming a dielectric layer of the trench capacitor; and forming a second electrode of the trench capacitor in the trench. The buried isolation layer intersects with the trench and has one or more gaps for providing body contact between a first substrate area above the buried isolation layer and a second substrate area below the buried isolation layer.
摘要翻译：形成沟槽电容器的方法包括：去除衬底的一部分以在衬底内形成沟槽; 在衬底内的掩埋隔离层处形成; 在所述衬底中至少在围绕所述沟槽的下部的区域中在所述沟槽电容器中形成第一电极; 形成沟槽电容器的电介质层; 以及在所述沟槽中形成所述沟槽电容器的第二电极。掩埋隔离层与沟槽相交并且具有一个或多个间隙，用于在掩埋隔离层之上的第一衬底区域和掩埋隔离层下面的第二衬底区域之间提供身体接触。

10. 发明申请

US20050062089A1 DRAM STRUCTURE AND FABRICATING METHOD THEREOF 失效
标题翻译： DRAM结构及其制作方法
公开(公告)号：US20050062089A1
公开(公告)日：2005-03-24
申请号：US10711623
申请日：2004-09-29
申请人： Yueh-Chuan Lee , Shih-Lung Chen
发明人： Yueh-Chuan Lee , Shih-Lung Chen
IPC分类号： H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/10873 , H01L29/66181 , H01L29/945
摘要： A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure. The doped region is formed in a self-aligned process by conducting a tilt implantation implanting ions into the substrate through the upper portion of the capacitor trench adjacent to the channel region after forming the trench but before the definition of the active region.
摘要翻译：提供了一种动态随机存取存储器（DRAM）结构及其制造方法。在制造过程中，在与隔离结构相邻的部分中，沟道区域形成有与衬底相同的导电性的掺杂区域。通过在形成沟槽之后但在有源区的定义之前，通过在邻近沟道区的电容器沟槽的上部通过进行倾斜注入而将离子注入到衬底中来形成掺杂区。

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