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1. 发明授权

US09047139B2 Primitives for software transactional memory 有权
标题翻译：软件事务内存的基本原理
公开(公告)号：US09047139B2
公开(公告)日：2015-06-02
申请号：US12163402
申请日：2008-06-27
申请人： Yosseff Levanoni , David L. Detlefs , Michael M. Magruder , Vinod K. Grover
发明人： Yosseff Levanoni , David L. Detlefs , Michael M. Magruder , Vinod K. Grover
IPC分类号： G06F17/30 , G06F9/52
CPC分类号： G06F9/528
摘要： Software transactional memory (STM) primitives are provided that allow the results of prior open calls to be used by subsequent open calls either as-is or through another STM primitive that consumes the results of the previous invocation. The STM primitives are configured to ensure that the address of a shadow copy representing a memory location will not changed across a wide range of operations and thereby enable re-use of the shadow copy.
摘要翻译：提供了软件事务存储器（STM）原语，其允许先前的打开调用的结果被按照原样或通过消耗先前调用的结果的另一个STM原语的后续打开调用来使用。 STM原语配置为确保表示内存位置的卷影副本的地址不会在广泛的操作范围内发生变化，从而可以重新使用卷影副本。

2. 发明授权

US08769514B2 Detecting race conditions with a software transactional memory system 有权
标题翻译：使用软件事务内存系统检测竞争条件
公开(公告)号：US08769514B2
公开(公告)日：2014-07-01
申请号：US12163902
申请日：2008-06-27
申请人： David L. Detlefs , Michael M. Magruder , Yosseff Levanoni
发明人： David L. Detlefs , Michael M. Magruder , Yosseff Levanoni
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F11/3624
摘要： A dynamic race detection system is provided that detects race conditions in code that executes concurrently in a computer system. The dynamic race detection system uses a modified software transactional memory (STM) system to detect race conditions. A compiler converts portions of the code that are not configured to operate with the STM system into pseudo STM code that operates with the STM system. The dynamic race detection system detects race conditions in response to either a pseudo STM transaction in the pseudo STM code failing to validate when executed or an actual STM transaction failing to validate when executed because of conflict with a concurrent pseudo STM transaction.
摘要翻译：提供了一种动态竞争检测系统，其检测在计算机系统中并发执行的代码中的竞争条件。动态竞争检测系统使用修改后的软件事务存储器（STM）系统来检测竞争条件。编译器将未配置为与STM系统一起运行的代码部分转换为与STM系统一起运行的伪STM代码。动态竞争检测系统响应于伪STM代码中的伪STM事务在执行时无法验证或由于与并发的伪STM事务冲突而被执行时实际的STM事务失败而检测到竞争条件。

3. 发明授权

US08688921B2 STM with multiple global version counters 有权
标题翻译： STM具有多个全局版本计数器
公开(公告)号：US08688921B2
公开(公告)日：2014-04-01
申请号：US12396560
申请日：2009-03-03
申请人： Yosseff Levanoni
发明人： Yosseff Levanoni
IPC分类号： G06F12/00
CPC分类号： G06F9/467
摘要： A software transactional memory system is provided with multiple global version counters. The system assigns an affinity to one of the global version counters for each thread that executes transactions. Each thread maintains a local copy of the global version counters for use in validating read accesses of transactions. Each thread uses a corresponding affinitized global version counter to store version numbers of write accesses of executed transactions. The system adaptively changes the affinities of threads when data conflict or global version counter conflict is detected between threads.
摘要翻译：软件事务内存系统提供有多个全局版本计数器。系统为执行事务的每个线程分配一个全局版本计数器的关联。每个线程都维护全局版本计数器的本地副本，以用于验证事务的读取访问。每个线程使用相应的关联全局版本计数器来存储已执行事务的写入访问的版本号。当在线程之间检测到数据冲突或全局版本计数器冲突时，系统自适应地改变线程的亲和性。

4. 发明授权

US08589867B2 Compiler-generated invocation stubs for data parallel programming model 有权
标题翻译：用于数据并行编程模型的编译器生成的调用存根
公开(公告)号：US08589867B2
公开(公告)日：2013-11-19
申请号：US12819108
申请日：2010-06-18
申请人： Lingli Zhang , Weirong Zhu , Yosseff Levanoni , Paul F. Ringseth , Charles David Callahan, II
发明人： Lingli Zhang , Weirong Zhu , Yosseff Levanoni , Paul F. Ringseth , Charles David Callahan, II
IPC分类号： G06F9/44
CPC分类号： G06F8/45
摘要： Described herein are techniques for generating invocation stubs for a data parallel programming model so that a data parallel program written in a statically-compiled high-level programming language may be more declarative, reusable, and portable than traditional approaches. With some of the described techniques, invocation stubs are generated by a compiler and those stubs bridge a logical arrangement of data parallel computations to the actual physical arrangement of a target data parallel hardware for that data parallel computation.
摘要翻译：这里描述的是用于生成用于数据并行编程模型的调用存根的技术，使得以静态编译的高级编程语言编写的数据并行程序可以比传统方法更具声明性，可重复使用和便携式。利用一些所描述的技术，调用存根由编译器生成，并且这些存根将数据并行计算的逻辑排列与用于该数据并行计算的目标数据并行硬件的实际物理排列相结合。

5. 发明授权

US08539458B2 Transforming addressing alignment during code generation 有权
标题翻译：在代码生成期间转换寻址对齐
公开(公告)号：US08539458B2
公开(公告)日：2013-09-17
申请号：US13158077
申请日：2011-06-10
申请人： Weirong Zhu , Yosseff Levanoni
发明人： Weirong Zhu , Yosseff Levanoni
IPC分类号： G06F9/44 , G06F9/45 , G06F7/38 , G06F9/00
CPC分类号： G06F8/44
摘要： The present invention extends to methods, systems, and computer program products for changing addressing mode during code generation. Generally, embodiments of the invention use a compiler transformation to transform lower level code from one address alignment to another address alignment. The transformation can be based upon assumptions of a source programming language. Based on the assumptions, the transformation can eliminate arithmetic operations that compensate for different addressing alignment, resulting in more efficient code. Some particular embodiments use a compiler transformation to transform an Intermediate Representation (“IR”) from one-byte addressing alignment into multi-byte (e.g., four-byte) addressing alignment.
摘要翻译：本发明扩展到用于在代码生成期间改变寻址模式的方法，系统和计算机程序产品。通常，本发明的实施例使用编译器转换来将较低级别的代码从一个地址对齐转换到另一个地址对齐。转换可以基于源程序设计语言的假设。基于这些假设，转换可以消除补偿不同寻址对齐的算术运算，从而产生更有效的代码。一些特定实施例使用编译器变换将中间表示（“IR”）从一字节寻址对准转换为多字节（例如，四字节）寻址对齐。

6. 发明授权

US08402218B2 Efficient garbage collection and exception handling in a hardware accelerated transactional memory system 有权
标题翻译：在硬件加速事务内存系统中高效的垃圾回收和异常处理
公开(公告)号：US08402218B2
公开(公告)日：2013-03-19
申请号：US12638929
申请日：2009-12-15
申请人： Jan Gray , Martin Taillefer , Yosseff Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod K. Grover , Michael Magruder , Gad Sheaffer
发明人： Jan Gray , Martin Taillefer , Yosseff Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod K. Grover , Michael Magruder , Gad Sheaffer
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/466 , G06F9/3004 , G06F9/30087 , G06F9/30185 , G06F9/3834 , G06F9/467 , G06F12/0253 , G06F12/0815 , G06F12/082
摘要： Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. Embodiments includes acts for writing to a card table outside of a transaction; handling garbage collection compaction occurring when a hardware transaction is active by using a common global variable and instructing one or more agents to write to the common global variable any time an operation is performed which may change an object's virtual address; acts for managing a thread-local allocation context; acts for handling exceptions while in a hardware assisted transaction. A method includes beginning a hardware assisted transaction, raising an exception while in the hardware assisted transaction, including creating an exception object, determining that the transaction should be rolled back, and as a result of determining that the transaction should be rolled back, marshaling the exception object out of the hardware assisted transaction.
摘要翻译：在硬件辅助交易中处理垃圾收集和异常。实施例在包括硬件辅助交易系统的计算环境中实现。实施例包括用于在事务之外写入卡表的动作; 通过使用公共全局变量来处理在硬件事务处于活动状态时发生的垃圾收集压缩，并且在每次执行可能改变对象的虚拟地址的操作时，指示一个或多个代理写入公共全局变量; 用于管理线程本地分配上下文的动作; 在硬件辅助交易中处理异常的行为。一种方法包括开始硬件辅助事务，在硬件辅助事务中引发异常，包括创建异常对象，确定事务应该回滚，并且由于确定事务应该回滚，因此，异常对象出来的硬件辅助事务。

7. 发明授权

US08341133B2 Compressed transactional locks in object headers 有权
标题翻译：对象标题中的压缩事务锁
公开(公告)号：US08341133B2
公开(公告)日：2012-12-25
申请号：US12163788
申请日：2008-06-27
申请人： David L. Detlefs , Vinod K. Grover , Yosseff Levanoni , Michael M. Magruder
发明人： David L. Detlefs , Vinod K. Grover , Yosseff Levanoni , Michael M. Magruder
IPC分类号： G06F7/00 , G06F17/00 , G06F13/00 , G06F13/28 , G06F15/16
CPC分类号： G06F9/466
摘要： A software transactional memory system is provided that generates and stores compressed transactional locks in a portion of object headers. The software transactional memory system allocates preferred write log memory with a predefined size of memory that corresponds to a number of bits in the compressed transactional locks. The compressed transactional locks identify write log entries in corresponding write logs in the preferred write log memory. If the preferred write log memory becomes full, additional write log memory is allocated for write log entries and subsequent transactional locks are stored uncompressed in an auxiliary memory. A pointer that may be used to locate the uncompressed transactional lock is stored in the header. If an object header with a compressed transactional lock is needed for another use, the compressed transactional lock is uncompressed and stored in the auxiliary memory. A pointer that may be used to locate the uncompressed transactional lock is stored in the header.
摘要翻译：提供了一种软件事务存储器系统，其在对象头部的一部分中生成并存储压缩事务锁。软件事务存储系统将优选的写日志存储器与对应于压缩事务锁中的多个位的预定义大小的存储器分配。压缩事务锁在首选写入日志存储器中的相应写入日志中标识写入日志条目。如果首选的写入日志内存已满，则会为写入日志条目分配额外的写入日志内存，而后续的事务锁存在未压缩的辅助存储器中。可用于定位未压缩事务锁的指针存储在标题中。如果需要具有压缩事务锁定的对象标头进行另一次使用，压缩事务锁将被解压缩并存储在辅助存储器中。可用于定位未压缩事务锁的指针存储在标题中。

8. 发明申请

US20120159458A1 RECONSTRUCTING PROGRAM CONTROL FLOW 有权
标题翻译：重新编制程序控制流程
公开(公告)号：US20120159458A1
公开(公告)日：2012-06-21
申请号：US12972198
申请日：2010-12-17
申请人： Yosseff Levanoni , Weirong Zhu , Lingli Zhang , John Lee Rapp , Andrew L. Bliss
发明人： Yosseff Levanoni , Weirong Zhu , Lingli Zhang , John Lee Rapp , Andrew L. Bliss
IPC分类号： G06F9/45
CPC分类号： G06F8/51 , G06F8/53
摘要： The present invention extends to methods, systems, and computer program products for reconstructing program control flow. Embodiments include implementing or morphing a control flow graph (“CFG”) into an arbitrary loop structure to reconstruct (preserve) control flow from original source code. Loop structures can be optimized and can adhere to target platform constraints. In some embodiments, C++ source code (a first higher level format) is translated into a CFG (a lower level format). The CFG is then translated into HLSL source code (a second different higher level format) for subsequent compilation into SLSL bytecode (that can then be executed at a Graphical Processing Unit (“GPU”)). The control flow from the C++ source code is preserved in the HLSL source code.
摘要翻译：本发明扩展到用于重建程序控制流的方法，系统和计算机程序产品。实施例包括将控制流程图（“CFG”）实现或变形为任意循环结构，以重构（保留）来自原始源代码的控制流程。循环结构可以进行优化，并可以遵守目标平台约束。在一些实施例中，将C ++源代码（第一较高级格式）转换成CFG（较低级格式）。然后将CFG转换为HLSL源代码（第二种不同的较高级别格式），以便后续编译成SLSL字节码（然后可以在图形处理单元（“GPU”）中执行）。来自C ++源代码的控制流将保留在HLSL源代码中。

9. 发明申请

US20110314230A1 ACTION FRAMEWORK IN SOFTWARE TRANSACTIONAL MEMORY 有权
标题翻译：软件交易记忆中的动作框架
公开(公告)号：US20110314230A1
公开(公告)日：2011-12-22
申请号：US12819494
申请日：2010-06-21
申请人： Lingli Zhang , Yosseff Levanoni , David L. Detlefs , Sukhdeep S. Sodhi , Weirong Zhu
发明人： Lingli Zhang , Yosseff Levanoni , David L. Detlefs , Sukhdeep S. Sodhi , Weirong Zhu
IPC分类号： G06F12/00 , G06F17/30
CPC分类号： G06F9/467 , G06F9/526
摘要： A software transactional memory system implements a lightweight key-based action framework. The framework includes a set of unified application programming interfaces (APIs) exposed by an STM library that allow clients to implement actions that can be registered, queried, and updated using specific keys by transactions or transaction nests in STM code. Each action includes a key, state information, and a set of one or more callbacks that can be hooked to the validation, commit, abort, and/or re-execution phases of transaction execution. The actions extend the built-in concurrency controls of the STM system with customized control logics, support transaction nesting semantics, and enable integration with garbage collection systems.
摘要翻译：软件事务内存系统实现了一个轻量级的基于键盘的动作框架。该框架包括由STM库公开的一组统一的应用程序编程接口（API），允许客户端通过STM代码中的事务处理或事务处理实现使用特定密钥进行注册，查询和更新的操作。每个动作包括一个密钥，状态信息和一组可以挂接到事务执行的验证，提交，中止和/或重新执行阶段的回调。该操作通过定制的控制逻辑扩展了STM系统的内置并发控制，支持事务嵌套语义，并实现了与垃圾收集系统的集成。

10. 发明申请

US20110145802A1 ACCELERATING UNBOUNDED MEMORY TRANSACTIONS USING NESTED CACHE RESIDENT TRANSACTIONS 有权
标题翻译：使用嵌入式高速缓存交易来加速无关紧要的存储交易
公开(公告)号：US20110145802A1
公开(公告)日：2011-06-16
申请号：US12638103
申请日：2009-12-15
申请人： Yosseff Levanoni , Gad Sheaffer , Ali-Reza Adl-Tabatabai
发明人： Yosseff Levanoni , Gad Sheaffer , Ali-Reza Adl-Tabatabai
IPC分类号： G06F9/45 , G06F9/46 , G06F12/00 , G06F12/08
CPC分类号： G06F9/467
摘要： Using cache resident transaction hardware to accelerate a software transactional memory system. The method includes identifying a plurality of atomic operations intended to be performed by a software transactional memory system as transactional operations as part of a software transaction. The method further includes selecting at least a portion of the plurality of atomic operations. The method further includes attempting to perform the portion of the plurality of atomic operations as hardware transactions using cache resident transaction hardware.
摘要翻译：使用缓存驻留交易硬件来加速软件事务内存系统。该方法包括将期望由软件事务存储器系统执行的多个原子操作识别为作为软件事务的一部分的事务操作。该方法还包括选择多个原子操作的至少一部分。该方法还包括尝试使用高速缓存驻留交易硬件来执行多个原子操作的部分作为硬件事务。

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