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    • 1. 发明授权
    • Received data processing apparatus of photoacoustic tomography
    • 光声层析成像的接收数据处理装置
    • US09247923B2
    • 2016-02-02
    • US13055632
    • 2009-09-03
    • Yoshitaka BabaHaruo YodaKazuhiko Fukutani
    • Yoshitaka BabaHaruo YodaKazuhiko Fukutani
    • A61B13/00A61B8/13A61B5/00A61B8/08
    • A61B5/0095A61B5/0073A61B5/7225A61B5/7278A61B8/13A61B8/483
    • There is provided a received data processing apparatus of photoacoustic tomography including a minimum constitution unit data composition unit that sequentially reads receiving digital signals from first storage units and composes minimum constitution unit data of the acoustic wave of the minimum constitution units by performing a delay-and-sum processing. A second storage unit stores the minimum constitution unit data of the entire region of the specimen, and an image construction unit constructs an image of the specimen based on the minimum constitution unit data stored in the second storage unit. A control unit sequentially stores the minimum constitution unit data calculated by the minimum constitution unit data composition unit in the second storage unit and reads the stored minimum constitution unit data of the entire region of the specimen to transmit the minimum constitution unit data to the image construction unit.
    • 提供了一种光声层析成像的接收数据处理装置,包括:最小构成单元数据合成单元,其顺序地从第一存储单元读取接收数字信号,并通过执行延迟来构成最小构成单元的声波的最小构成单位数据; -sum处理。 第二存储单元存储样本的整个区域的最小构成单位数据,图像构造单元基于存储在第二存储单元中的最小构成单位数据构建样本的图像。 控制单元将由最小构成单位数据构成单元计算出的最小构成单位数据顺序地存储在第二存储单元中,并读取所存储的样本的整个区域的最小构成单位数据,将最小构成单位数据发送到图像构造 单元。
    • 8. 发明申请
    • Twin MONOS array for high speed application
    • 双MONOS阵列用于高速应用
    • US20080186763A1
    • 2008-08-07
    • US12079966
    • 2008-03-31
    • Kimihiro SatohTomoko OgubaKi-Tae ParkNori OguraYoshitaka Baba
    • Kimihiro SatohTomoko OgubaKi-Tae ParkNori OguraYoshitaka Baba
    • G11C11/409H01L23/528
    • G11C16/08G11C16/0466G11C16/16H01L29/792
    • A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.
    • 双MONOS金属位阵列的字栅和控制栅的针迹区域配置包括在字门的侧壁上的控制栅极,其中字栅和控制栅并联运行。 控制栅极多晶硅触点在垂直于控制栅极的针脚区域处接触排列成一排的控制栅极。 缝合区域的两个字门多晶硅接点交替字门。 还提供了位线,字线和控制门解码器和驱动器,位线解码器,位线控制电路和用于控制存储器阵列的芯片控制器。 本发明还提供双MONOS金属位阵列操作,其包括由一个控制栅极驱动电路驱动的多个控制栅极和由一个字栅极驱动器电路驱动的一个字栅极以及擦除禁止和块擦除。