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1. 发明授权

US07352033B2 Twin MONOS array for high speed application 有权
标题翻译：双MONOS阵列用于高速应用
公开(公告)号：US07352033B2
公开(公告)日：2008-04-01
申请号：US11215528
申请日：2005-08-30
申请人： Kimihiro Satoh , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Yoshitaka Baba
发明人： Kimihiro Satoh , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Yoshitaka Baba
IPC分类号： H01L29/772
CPC分类号： G11C16/08 , G11C16/0466 , G11C16/16 , H01L29/792
摘要： The invention provides a metal bit structure of Twin MONOS memory cell with large channel width and its operational method for high-speed applications using a metal bit array.
摘要翻译：本发明提供了具有大通道宽度的双MONOS存储单元的金属钻头结构及其使用金属钻头阵列的高速应用的操作方法。

2. 发明授权

US08633544B2 Twin MONOS array for high speed application 有权
标题翻译：双MONOS阵列用于高速应用
公开(公告)号：US08633544B2
公开(公告)日：2014-01-21
申请号：US12079966
申请日：2008-03-31
申请人： Kimihiro Satoh , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Yoshitaka Baba
发明人： Kimihiro Satoh , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Yoshitaka Baba
IPC分类号： H01L29/772
CPC分类号： G11C16/08 , G11C16/0466 , G11C16/16 , H01L29/792
摘要： A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.
摘要翻译：双MONOS金属位阵列的字栅和控制栅的针迹区域配置包括在字门的侧壁上的控制栅极，其中字栅和控制栅并联运行。控制栅极多晶硅触点在垂直于控制栅极的针脚区域处接触排列成一排的控制栅极。缝合区域的两个字门多晶硅接点交替字门。还提供了位线，字线和控制门解码器和驱动器，位线解码器，位线控制电路和用于控制存储器阵列的芯片控制器。本发明还提供双MONOS金属位阵列操作，其包括由一个控制栅极驱动电路驱动的多个控制栅极和由一个字栅极驱动器电路驱动的一个字栅极以及擦除禁止和块擦除。

3. 发明申请

US20070047309A1 Twin MONOS array for high speed application 有权
标题翻译：双MONOS阵列用于高速应用
公开(公告)号：US20070047309A1
公开(公告)日：2007-03-01
申请号：US11215528
申请日：2005-08-30
申请人： Kimihiro Satoh , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Yoshitaka Baba
发明人： Kimihiro Satoh , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Yoshitaka Baba
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C16/0466 , G11C16/16 , H01L29/792
摘要： The invention provides a metal bit structure of Twin MONOS memory cell with large channel width and its operational method for high-speed applications using a metal bit array.
摘要翻译：本发明提供了具有大通道宽度的双MONOS存储单元的金属钻头结构及其使用金属钻头阵列的高速应用的操作方法。

4. 发明授权

US07190603B2 Nonvolatile memory array organization and usage 有权
标题翻译：非易失性存储器阵列的组织和使用
公开(公告)号：US07190603B2
公开(公告)日：2007-03-13
申请号：US11124221
申请日：2005-05-06
申请人： Seiki Ogura , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C5/06
CPC分类号： G11C16/0475 , G11C5/025 , G11C16/16 , G11C16/24 , H01L27/115
摘要： A non-volatile semiconductor storage device array organization for wide program operations is achieved. The device includes a memory cell array region in which a plurality of C columns and R rows of memory cells comprise one UNIT, arranged in a “diffusion bit” array organization which is comprised of R rows of word lines running in a first direction, and C columns of diffusion sub bit lines running in a second direction, and C columns of sub control gate lines running in the same second direction and a sense amplifier/page buffer area shared by several UNIT's through a bit decode circuit, wherein the diffusion sub bit lines in each of the UNIT's are connected to main bit lines which are in turn connected to the sense amplifier/page buffer area, wherein the bit decode circuit selects one diffusion sub bit line column of memory cells in every E columns.
摘要翻译：实现了用于广泛程序操作的非易失性半导体存储器件阵列组织。该装置包括一个存储单元阵列区域，其中多个C列和R行的存储单元包括一个单元，以“扩散位”阵列组织排列，该阵列组织由沿第一方向运行的R行字线组成，以及 C列的第二方向上延伸的扩散子位线，以及在相同的第二方向上运行的子控制栅极线的C列以及由多个单元通过位解码电路共享的读出放大器/页缓冲区，其中扩散子位每个单元中的线连接到主位线，主位线又连接到读出放大器/页面缓冲区域，其中位解码电路在每个E列中选择存储器单元的一个扩散子位线列。

5. 发明申请

US20050248984A1 Nonvolatile memory array organization and usage 有权
标题翻译：非易失性存储器阵列的组织和使用
公开(公告)号：US20050248984A1
公开(公告)日：2005-11-10
申请号：US11124221
申请日：2005-05-06
申请人： Seiki Ogura , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C5/02 , G11C16/04 , G11C16/16 , G11C16/24 , H01L27/115
CPC分类号： G11C16/0475 , G11C5/025 , G11C16/16 , G11C16/24 , H01L27/115
摘要： A non-volatile semiconductor storage device array organization for wide program operations is achieved. The device comprises a memory cell array region in which a plurality of C columns and R rows of memory cells comprise one UNIT, arranged in a “diffusion bit” array organization which is comprised of R rows of word lines running in a first direction, and C columns of diffusion sub bit lines running in a second direction, and C columns of sub control gate lines running in the same second direction and a sense amplifier/page buffer area shared by several UNIT's through a bit decode circuit, wherein the diffusion sub bit lines in each of the UNIT's are connected to main bit lines which are in turn connected to the sense amplifier/page buffer area, wherein the bit decode circuit selects one diffusion sub bit line column of memory cells in every E columns.
摘要翻译：实现了用于广泛程序操作的非易失性半导体存储器件阵列组织。该装置包括存储单元阵列区域，其中多个C列和R行存储单元包括一个单元，以“扩散位”阵列组织排列，该阵列组织包括沿第一方向运行的R行字线，以及 C列的第二方向上延伸的扩散子位线，以及在相同的第二方向上运行的子控制栅极线的C列以及由多个单元通过位解码电路共享的读出放大器/页缓冲区，其中扩散子位每个单元中的线连接到主位线，主位线又连接到读出放大器/页面缓冲区域，其中位解码电路在每个E列中选择存储器单元的一个扩散子位线列。

6. 发明申请

US20080186763A1 Twin MONOS array for high speed application 有权
标题翻译：双MONOS阵列用于高速应用
公开(公告)号：US20080186763A1
公开(公告)日：2008-08-07
申请号：US12079966
申请日：2008-03-31
申请人： Kimihiro Satoh , Tomoko Oguba , Ki-Tae Park , Nori Ogura , Yoshitaka Baba
发明人： Kimihiro Satoh , Tomoko Oguba , Ki-Tae Park , Nori Ogura , Yoshitaka Baba
IPC分类号： G11C11/409 , H01L23/528
CPC分类号： G11C16/08 , G11C16/0466 , G11C16/16 , H01L29/792
摘要： A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.
摘要翻译：双MONOS金属位阵列的字栅和控制栅的针迹区域配置包括在字门的侧壁上的控制栅极，其中字栅和控制栅并联运行。控制栅极多晶硅触点在垂直于控制栅极的针脚区域处接触排列成一排的控制栅极。缝合区域的两个字门多晶硅接点交替字门。还提供了位线，字线和控制门解码器和驱动器，位线解码器，位线控制电路和用于控制存储器阵列的芯片控制器。本发明还提供双MONOS金属位阵列操作，其包括由一个控制栅极驱动电路驱动的多个控制栅极和由一个字栅极驱动器电路驱动的一个字栅极以及擦除禁止和块擦除。

7. 发明申请

US20070030745A1 Referencing scheme for trap memory 有权
标题翻译：陷阱内存引用方案
公开(公告)号：US20070030745A1
公开(公告)日：2007-02-08
申请号：US11500115
申请日：2006-08-07
申请人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Yoshitaka Baba
发明人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Yoshitaka Baba
IPC分类号： G11C7/02 , G11C16/06 , G11C11/34
CPC分类号： G11C7/14 , G11C16/0475 , G11C16/28 , G11C16/3445 , G11C16/3454 , G11C16/3459
摘要： A reference circuit is described for creating a reference signal using a twin MONOS memory cell. A first portion of the twin MONOS memory cell connects to a charged and floating bit line a current source formed in a second portion of the twin MONOS cell that discharges the charged bit line to form a reference signal for a sense amplifier. The sense amplifier compares the reference signal to a signal from a selected memory cell upon which memory operations are being performed comprising read, erase verify and program verify.
摘要翻译：描述了使用双MONOS存储单元创建参考信号的参考电路。双MONOS存储器单元的第一部分连接到充电和浮置位线，形成在双MONOS单元的第二部分中的电流源，其对充电的位线进行放电以形成用于读出放大器的参考信号。读出放大器将参考信号与来自执行存储器操作的所选存储器单元的信号进行比较，包括读取，擦除验证和程序验证。

8. 发明申请

US20070047307A1 High speed operation method for twin MONOS metal bit array 有权
标题翻译：双MONOS金属钻头阵列的高速运行方式
公开(公告)号：US20070047307A1
公开(公告)日：2007-03-01
申请号：US11215418
申请日：2005-08-30
申请人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
发明人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.
摘要翻译：本发明提供了一种用于高速应用的双MONOS金属钻头或扩散钻头结构的新颖操作方法。在本发明的第一实施例中，替代控制栅极被设置在相同的电压。在本发明的第二实施例中，所有的控制栅极都从一开始就被设定为工作电压。在两个实施例中，位线和字门被用于寻址选定的存储单元。

9. 发明授权

US08174885B2 High speed operation method for twin MONOS metal bit array 有权
标题翻译：双MONOS金属钻头阵列的高速运行方式
公开(公告)号：US08174885B2
公开(公告)日：2012-05-08
申请号：US13068066
申请日：2011-05-02
申请人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
发明人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
IPC分类号： G11C11/34
CPC分类号： G11C16/0475
摘要： The present invention provides a novel read method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.teh
摘要翻译：本发明提供了一种用于高速应用的双MONOS金属钻头或扩散钻头结构的新型读取方法。在本发明的第一实施例中，替代控制栅极被设置在相同的电压。在本发明的第二实施例中，所有的控制栅极都从一开始就被设定为工作电压。在两个实施例中，位线和字门用于对选定的存储单元进行寻址

10. 发明授权

US07447077B2 Referencing scheme for trap memory 有权
标题翻译：陷阱内存引用方案
公开(公告)号：US07447077B2
公开(公告)日：2008-11-04
申请号：US11500115
申请日：2006-08-07
申请人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Yoshitaka Baba
发明人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Yoshitaka Baba
IPC分类号： G11C11/34
CPC分类号： G11C7/14 , G11C16/0475 , G11C16/28 , G11C16/3445 , G11C16/3454 , G11C16/3459
摘要： A reference circuit is described for creating a reference signal using a twin MONOS memory cell. A first portion of the twin MONOS memory cell connects to a charged and floating bit line a current source formed in a second portion of the twin MONOS cell that discharges the charged bit line to form a reference signal for a sense amplifier. The sense amplifier compares the reference signal to a signal from a selected memory cell upon which memory operations are being performed comprising read, erase verify and program verify.
摘要翻译：描述了使用双MONOS存储单元创建参考信号的参考电路。双MONOS存储器单元的第一部分连接到充电和浮置位线，形成在双MONOS单元的第二部分中的电流源，其对充电的位线进行放电以形成用于读出放大器的参考信号。读出放大器将参考信号与来自执行存储器操作的所选存储器单元的信号进行比较，包括读取，擦除验证和程序验证。

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