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1. 发明申请

US20100102382A1 TRENCH GATE TYPE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： TRENCH门式晶体管及其制造方法
公开(公告)号：US20100102382A1
公开(公告)日：2010-04-29
申请号：US12447817
申请日：2008-09-26
申请人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
发明人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66734 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/513 , H01L29/66348 , H01L29/7397 , H01L29/7809 , H01L29/7813
摘要： The invention provides a trench gate type transistor in which the gate leakage current is prevented and the gate capacitance is reduced. A trench is formed in an N− type semiconductor layer. A thin silicon oxide film is formed on a region of the N− type semiconductor layer for the active region of the transistor in the trench. On the other hand, a silicon oxide film which is thicker than the silicon oxide film is formed on a region not for the active region. Furthermore, a leading portion extending from inside the trench onto the outside thereof forms a gate electrode contacting the silicon oxide film. This provides a long distance between the gate electrode at the leading portion and the corner portion of the N− type semiconductor layer, thereby preventing the gate leakage current and reducing the gate capacitance.
摘要翻译：本发明提供了一种沟槽栅型晶体管，其中栅极漏电流被防止并且栅极电容减小。在N型半导体层中形成沟槽。在沟槽中的晶体管的有源区域的N型半导体层的区域上形成薄的氧化硅膜。另一方面，在不是有源区的区域上形成比氧化硅膜厚的氧化硅膜。此外，从沟槽内部延伸到其外部的引导部分形成与氧化硅膜接触的栅电极。这提供了在前导部分的栅电极和N-型半导体层的角部之间的长距离，从而防止栅极漏电流并降低栅极电容。

2. 发明授权

US07646062B2 Semiconductor device comprising buried wiring layer 有权
标题翻译：包括掩埋布线层的半导体器件
公开(公告)号：US07646062B2
公开(公告)日：2010-01-12
申请号：US11770337
申请日：2007-06-28
申请人： Yoshikazu Yamaoka , Satoru Shimada
发明人： Yoshikazu Yamaoka , Satoru Shimada
IPC分类号： H01L27/01 , H01L27/12 , H01L27/10 , H01L29/73 , H01L29/74 , H01L27/148 , H01L29/749 , H01L29/768 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/7816 , H01L21/28114 , H01L29/42376 , H01L29/4238 , H01L29/66553 , H01L29/66621
摘要： A semiconductor device that suppresses partial discharging to a semiconductor substrate caused by local concentration of current. The semiconductor device includes a semiconductor substrate, a gate electrode buried in the semiconductor substrate, a conductor buried in the semiconductor substrate further inward from the gate electrode, a wiring layer formed in the semiconductor substrate in connection with the conductor, and an insulation film arranged between the gate electrode and the conductor. The conductor is higher than the surface of the semiconductor substrate.
摘要翻译：一种半导体器件，其抑制由局部电流集中引起的对半导体衬底的局部放电。半导体器件包括半导体衬底，埋在半导体衬底中的栅电极，从栅电极进一步向内埋入半导体衬底中的导体，与该导体连接形成在该半导体衬底中的布线层，以及布置在绝缘膜上的绝缘膜在栅电极和导体之间。导体高于半导体衬底的表面。

3. 发明申请

US20070120203A1 Semiconductor device and method for manufacturing the semiconductor devices 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070120203A1
公开(公告)日：2007-05-31
申请号：US11604359
申请日：2006-11-27
申请人： Yoshikazu Yamaoka , Kazunori Fujita , Satoru Shimada , Hideki Mizuhara , Yasunori Inoue
发明人： Yoshikazu Yamaoka , Kazunori Fujita , Satoru Shimada , Hideki Mizuhara , Yasunori Inoue
IPC分类号： H01L29/76
CPC分类号： H01L21/28088 , H01L21/28114 , H01L21/28247 , H01L21/823842 , H01L21/823857 , H01L29/4966
摘要： A semiconductor device includes a semiconductor substrate on which a source region and a drain region are formed, an insulating film formed on the semiconductor substrate and interposed between the source region and the drain region, a gate electrode formed on the insulating film, metal-bearing particles formed on the interface between the insulation film and the gate electrode, and an insulator which has been changed from a part of metal-bearing particles protruding from an edge of the interface.
摘要翻译：半导体器件包括其上形成有源极区和漏极区的半导体衬底，形成在半导体衬底上且介于源极区和漏极区之间的绝缘膜，形成在绝缘膜上的栅电极，金属轴承形成在绝缘膜和栅电极之间的界面上的颗粒以及从界面边缘突出的一部分金属承载颗粒改变的绝缘体。

4. 发明授权

US08076720B2 Trench gate type transistor 有权
标题翻译：沟槽型晶体管
公开(公告)号：US08076720B2
公开(公告)日：2011-12-13
申请号：US12447817
申请日：2008-09-26
申请人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
发明人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66734 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/513 , H01L29/66348 , H01L29/7397 , H01L29/7809 , H01L29/7813
摘要： The invention provides a trench gate type transistor in which the gate leakage current is prevented and the gate capacitance is reduced. A trench is formed in an N− type semiconductor layer. A thin silicon oxide film is formed on a region of the N− type semiconductor layer for the active region of the transistor in the trench. On the other hand, a silicon oxide film which is thicker than the silicon oxide film is formed on a region not for the active region. Furthermore, a leading portion extending from inside the trench onto the outside thereof forms a gate electrode contacting the silicon oxide film. This provides a long distance between the gate electrode at the leading portion and the corner portion of the N− type semiconductor layer, thereby preventing the gate leakage current and reducing the gate capacitance.
摘要翻译：本发明提供了一种沟槽栅型晶体管，其中栅极漏电流被防止并且栅极电容减小。在N型半导体层中形成沟槽。在沟槽中的晶体管的有源区域的N型半导体层的区域上形成薄的氧化硅膜。另一方面，在不是有源区的区域上形成比氧化硅膜厚的氧化硅膜。此外，从沟槽内部延伸到其外部的引导部分形成与氧化硅膜接触的栅电极。这提供了在前导部分的栅电极和N-型半导体层的角部之间的长距离，从而防止栅极漏电流并降低栅极电容。

5. 发明申请

US20130014810A1 PHOTOELECTRIC CONVERSION DEVICE 审中-公开
标题翻译：光电转换器件
公开(公告)号：US20130014810A1
公开(公告)日：2013-01-17
申请号：US13614788
申请日：2012-09-13
申请人： Yoshikazu YAMAOKA , Shigeo YATA
发明人： Yoshikazu YAMAOKA , Shigeo YATA
IPC分类号： H01L31/06
CPC分类号： H01L31/076 , Y02E10/548
摘要： In order to increase the photoelectric conversion efficiency of a photoelectric conversion device, a photoelectric conversion device (400), obtained by layering semiconductor layers consisting of a p-type layer (42), an i-type layer (46) and an n-type layer (50), is provided with a first intermediate layer (44) and a second intermediate layer (48), which abut the i-type layer (46) and have refractive indices that increase from the side that abuts the i-type layer (46) to the side that does not abut the i-type layer (46) within a range of refractive indices lower than that of the i-type layer.
摘要翻译：为了提高光电转换装置的光电转换效率，通过将由p型层（42），i型层（46）和n-型层构成的半导体层分层而获得的光电转换装置（400）型层（50）具有与i型层（46）抵接的第一中间层（44）和第二中间层（48），并且具有从与i型层层（46）在不比i型层的折射率低的范围内不与i型层（46）抵接的一侧。

6. 发明授权

US08319281B2 Semiconductor device with insulated gate formed within grooved portion formed therein 有权
标题翻译：具有绝缘栅的半导体器件形成在其中形成的沟槽部分内
公开(公告)号：US08319281B2
公开(公告)日：2012-11-27
申请号：US11965536
申请日：2007-12-27
申请人： Yoshikazu Yamaoka , Satoru Shimada , Kazunori Fujita , Kazuhiro Sasada
发明人： Yoshikazu Yamaoka , Satoru Shimada , Kazunori Fujita , Kazuhiro Sasada
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4236 , H01L21/2815 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7809 , H01L29/7813
摘要： A semiconductor device capable of inhibiting a fabricating process from complication while inhibiting the dielectric strength voltage of a insulating film from reduction is obtained. This semiconductor device includes a groove portion, an insulating film formed on a surface of the groove portion, a gate electrode and a source impurity region, wherein upper ends of the gate electrode, which are portions in contact with the insulating film, are each located at a position identical with or deeper than the range of an impurity introduced from a surface of a semiconductor substrate with respect to the insulating film in order to form the source impurity region and above a lower surface of the source impurity region.
摘要翻译：可以获得能够在抑制绝缘膜的介电强度电压降低的同时抑制制造工艺的复杂化的半导体器件。该半导体器件包括沟槽部分，形成在沟槽部分的表面上的绝缘膜，栅极电极和源极杂质区域，其中栅电极的与绝缘膜接触的部分的上端分别位于在与半导体衬底的表面相对于绝缘膜引入的杂质的范围相同或更深的位置处，以形成源极杂质区域和源极杂质区域的下表面之上。

7. 发明授权

US08242557B2 Trench gate type transistor 有权
标题翻译：沟槽型晶体管
公开(公告)号：US08242557B2
公开(公告)日：2012-08-14
申请号：US12447820
申请日：2008-09-26
申请人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
发明人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7809
摘要： The invention provides a trench gate type transistor in which the gate capacitance is reduced, the crystal defect is prevented and the gate breakdown voltage is enhanced. Trenches are formed in an N− type semiconductor layer. A uniformly thick silicon oxide film is formed on the bottom of each of the trenches and near the bottom, being round at corner portions. A silicon oxide film is formed on the upper portion of the sidewall of each of the trenches, which is thinner than the silicon oxide film and round at corner portions. Gate electrodes are formed from inside the trenches onto the outside thereof. The thick silicon oxide film reduces the gate capacitance, and the thin silicon oxide film on the upper portion provides good transistor characteristics. Furthermore, with the round corner portions, the crystal defect does not easily occur, and the gate electric field is dispersed to enhance the gate breakdown voltage.
摘要翻译：本发明提供一种沟槽栅型晶体管，其栅极电容减小，防止了晶体缺陷，提高了栅极击穿电压。沟槽形成在N-型半导体层中。在每个沟槽的底部和底部附近形成均匀厚的氧化硅膜，在角部处是圆形的。在每个沟槽的侧壁的上部形成氧化硅膜，其比氧化硅膜薄并且在角部处圆形。栅极电极从沟槽内部形成到其外部。厚的氧化硅膜减小栅极电容，并且上部的薄氧化硅膜提供良好的晶体管特性。此外，由于圆角部分不容易发生晶体缺陷，并且栅极电场被分散以提高栅极击穿电压。

8. 发明申请

US20100059816A1 TRENCH GATE TYPE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： TRENCH门式晶体管及其制造方法
公开(公告)号：US20100059816A1
公开(公告)日：2010-03-11
申请号：US12447820
申请日：2008-09-26
申请人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
发明人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7809
摘要： The invention provides a trench gate type transistor in which the gate capacitance is reduced, the crystal defect is prevented and the gate breakdown voltage is enhanced. Trenches are formed in an N− type semiconductor layer. A uniformly thick silicon oxide film is formed on the bottom of each of the trenches and near the bottom, being round at corner portions. A silicon oxide film is formed on the upper portion of the sidewall of each of the trenches, which is thinner than the silicon oxide film and round at corner portions. Gate electrodes are formed from inside the trenches onto the outside thereof. The thick silicon oxide film reduces the gate capacitance, and the thin silicon oxide film on the upper portion provides good transistor characteristics. Furthermore, with the round corner portions, the crystal defect does not easily occur, and the gate electric field is dispersed to enhance the gate breakdown voltage.
摘要翻译：本发明提供一种沟槽栅型晶体管，其栅极电容减小，防止了晶体缺陷，提高了栅极击穿电压。沟槽形成在N-型半导体层中。在每个沟槽的底部和底部附近形成均匀厚的氧化硅膜，在角部处是圆形的。在每个沟槽的侧壁的上部形成氧化硅膜，其比氧化硅膜薄并且在角部处圆形。栅极电极从沟槽内部形成到其外部。厚的氧化硅膜减小栅极电容，并且上部的薄氧化硅膜提供良好的晶体管特性。此外，由于圆角部分不容易发生晶体缺陷，并且栅极电场被分散以提高栅极击穿电压。

9. 发明申请

US20080001214A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080001214A1
公开(公告)日：2008-01-03
申请号：US11770337
申请日：2007-06-28
申请人： Yoshikazu Yamaoka , Satoru Shimada
发明人： Yoshikazu Yamaoka , Satoru Shimada
IPC分类号： H01L27/02 , H01L21/336
CPC分类号： H01L29/7816 , H01L21/28114 , H01L29/42376 , H01L29/4238 , H01L29/66553 , H01L29/66621
摘要： A semiconductor device that suppresses partial discharging to a semiconductor substrate caused by local concentration of current. The semiconductor device includes a semiconductor substrate, a gate electrode buried in the semiconductor substrate, a conductor buried in the semiconductor substrate further inward from the gate electrode, a wiring layer formed in the semiconductor substrate in connection with the conductor, and an insulation film arranged between the gate electrode and the conductor. The conductor is higher than the surface of the semiconductor substrate.
摘要翻译：一种半导体器件，其抑制由局部电流集中引起的对半导体衬底的局部放电。半导体器件包括半导体衬底，埋在半导体衬底中的栅电极，从栅电极进一步向内埋入半导体衬底中的导体，与该导体连接形成在该半导体衬底中的布线层，以及布置在绝缘膜上的绝缘膜在栅电极和导体之间。导体高于半导体衬底的表面。

10. 发明申请

US20070235812A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070235812A1
公开(公告)日：2007-10-11
申请号：US11729972
申请日：2007-03-30
申请人： Hideaki Fujiwara , Kazunori Fujita , Yoshikazu Yamaoka , Hideki Mizuhara , Yasunori Inoue
发明人： Hideaki Fujiwara , Kazunori Fujita , Yoshikazu Yamaoka , Hideki Mizuhara , Yasunori Inoue
IPC分类号： H01L23/62
CPC分类号： H01L29/792 , B82Y10/00 , G11C16/0408 , G11C2216/06 , H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/42348 , H01L29/6659 , H01L29/66833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device operating at low voltage is provided where a threshold voltage is controlled with ease. A semiconductor substrate is element-isolated by element isolation regions. A source region and a source region are spaced from each other on the semiconductor substrate. A gate electrode is formed between the source region and the drain by way of a gate insulator. A plurality of insulating particles are embedded in the gate electrode in a scattered manner at an interface between the gate insulator and the gate electrode, where the particles are in contact with the gate insulator.
摘要翻译：提供以低电压工作的半导体器件，其中容易地控制阈值电压。半导体衬底通过元件隔离区元件隔离。源极区域和源极区域在半导体衬底上彼此间隔开。通过栅极绝缘体在源区和漏极之间形成栅电极。多个绝缘颗粒以分散的方式嵌入在栅极绝缘体和栅电极之间的界面处，其中颗粒与栅极绝缘体接触。

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