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1. 发明申请

US20070235812A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070235812A1
公开(公告)日：2007-10-11
申请号：US11729972
申请日：2007-03-30
申请人： Hideaki Fujiwara , Kazunori Fujita , Yoshikazu Yamaoka , Hideki Mizuhara , Yasunori Inoue
发明人： Hideaki Fujiwara , Kazunori Fujita , Yoshikazu Yamaoka , Hideki Mizuhara , Yasunori Inoue
IPC分类号： H01L23/62
CPC分类号： H01L29/792 , B82Y10/00 , G11C16/0408 , G11C2216/06 , H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/42348 , H01L29/6659 , H01L29/66833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device operating at low voltage is provided where a threshold voltage is controlled with ease. A semiconductor substrate is element-isolated by element isolation regions. A source region and a source region are spaced from each other on the semiconductor substrate. A gate electrode is formed between the source region and the drain by way of a gate insulator. A plurality of insulating particles are embedded in the gate electrode in a scattered manner at an interface between the gate insulator and the gate electrode, where the particles are in contact with the gate insulator.
摘要翻译：提供以低电压工作的半导体器件，其中容易地控制阈值电压。半导体衬底通过元件隔离区元件隔离。源极区域和源极区域在半导体衬底上彼此间隔开。通过栅极绝缘体在源区和漏极之间形成栅电极。多个绝缘颗粒以分散的方式嵌入在栅极绝缘体和栅电极之间的界面处，其中颗粒与栅极绝缘体接触。

2. 发明授权

US08866194B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08866194B2
公开(公告)日：2014-10-21
申请号：US11902560
申请日：2007-09-24
申请人： Shinya Naito , Hideaki Fujiwara , Toru Dan
发明人： Shinya Naito , Hideaki Fujiwara , Toru Dan
IPC分类号： H01L29/66 , H01L27/06 , H01L21/8249 , H01L29/08 , H01L29/737 , H01L29/78
CPC分类号： H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/0821 , H01L29/66242 , H01L29/7378 , H01L29/78
摘要： A semiconductor device (npn bipolar transistor) includes an n-type collector layer, a base layer constituted by a p+ diffusion layer, a SiGe layer and a p-type silicon film, an n-type emitter layer and a charge transport prevention film formed between the n-type collector layer and the n-type emitter layer and having an effect as a potential barrier with respect to either electrons or holes.
摘要翻译：半导体器件（npn双极晶体管）包括n型集电极层，由p +扩散层，SiGe层和p型硅膜构成的基极层，形成n型发射极层和电荷传输防止膜在n型集电极层和n型发射极层之间，并且对于电子或空穴具有作为势垒的作用。

3. 发明授权

US08105060B2 Impact target capsule and impact compression apparatus 失效
标题翻译：冲击目标胶囊和冲击压缩装置
公开(公告)号：US08105060B2
公开(公告)日：2012-01-31
申请号：US12438046
申请日：2007-08-31
申请人： Hideharu Iwasaki , Takayuki Ikeda , Hideaki Fujiwara , Yoshihisa Tsuji
发明人： Hideharu Iwasaki , Takayuki Ikeda , Hideaki Fujiwara , Yoshihisa Tsuji
IPC分类号： B29C43/02
CPC分类号： G01N3/04 , B30B1/001 , G01N3/313 , G01N2203/0447
摘要： A target capsule includes (A) a pedestal having a central projection, (B) a pedestal aid attached to the central projection so as to define a sample-loading assembly, and (C) an impact-receiving member, wherein the components (A), (B), and (C) are detachable from each other. The impact target capsule can be readily loaded with a sample, allows the sample to be easily retrieved after application of impact pressure, and can be used repeatedly, and thereby the capsule can be preferably used as an impact compression apparatus in combination with a single-stage powder gun or a single-stage gas gun.
摘要翻译：目标胶囊包括（A）具有中心突起的基座，（B）附接到中心突起的基座辅助件，以便限定样品加载组件，和（C）冲击接收部件，其中部件（A ），（B）和（C）可以彼此分离。冲击目标胶囊可以容易地装载样品，允许在施加冲击压力之后容易地取出样品，并且可以重复使用，从而胶囊可以优选地用作冲击压缩装置，舞台粉枪或单级气枪。

4. 发明申请

US20050212038A1 Leakage control in semiconductor apparatus and fabricating method 审中-公开
标题翻译：半导体装置的漏电控制及其制造方法
公开(公告)号：US20050212038A1
公开(公告)日：2005-09-29
申请号：US11090009
申请日：2005-03-28
申请人： Hideaki Fujiwara
发明人： Hideaki Fujiwara
IPC分类号： H01L29/423 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/41 , H01L29/49 , H01L29/76 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66621 , H01L29/66545 , H01L29/66636 , H01L29/7834
摘要： A source region and a drain region spaced apart from each other are provided in a semiconductor substrate separating adjacent devices by shallow trench isolation (STI). The semiconductor substrate between the source region and the drain region is selectively removed so as to form a recess for a gate electrode. A recess for the gate electrode is formed in the recess. The gate electrode is formed in the recess via a gate insulating film and a gate coating. The underside of the gate insulating film is located below the underside of a source extension region and a drain region.
摘要翻译：在通过浅沟槽隔离（STI）分离相邻器件的半导体衬底中设置彼此间隔开的源极区域和漏极区域。选择性地去除源极区域和漏极区域之间的半导体衬底，以形成用于栅电极的凹部。在凹槽中形成用于栅电极的凹部。栅电极经由栅极绝缘膜和栅极涂层形成在凹部中。栅极绝缘膜的下侧位于源极延伸区域和漏极区域的下侧之下。

5. 发明授权

US07564106B2 Semiconductor device comprising gate electrode 有权
标题翻译：包括栅电极的半导体器件
公开(公告)号：US07564106B2
公开(公告)日：2009-07-21
申请号：US11711726
申请日：2007-02-28
申请人： Hideaki Fujiwara
发明人： Hideaki Fujiwara
IPC分类号： H01L29/78
CPC分类号： H01L21/28079 , H01L21/28035 , H01L21/823842 , H01L21/823857 , H01L21/823864
摘要： A semiconductor device capable of reducing a threshold voltage is obtained. The semiconductor device includes a pair of source/drain regions formed on the main surface of a semiconductor region to hold a channel region therebetween, and a gate electrode formed on the channel region through a gate insulating film and including a metal-containing layer arranged in the vicinity of an interface between the gate insulating film and the gate electrode, wherein the metal-containing layer is so formed in the form of dots as to partially cover the surface of the gate insulating film, and the average distance between dots forming the metal-containing layer is set to not more than a diameter of the dot of the metal-containing layer.
摘要翻译：获得能够降低阈值电压的半导体器件。半导体器件包括形成在半导体区域的主表面上以保持其间的沟道区的一对源极/漏极区，以及通过栅极绝缘膜形成在沟道区上的栅极，并且包括含有金属的层栅极绝缘膜和栅电极之间的界面附近，其中含金属层以点的形式形成为部分地覆盖栅极绝缘膜的表面，并且形成金属的点之间的平均距离含有层被设定为不大于含金属层的点的直径。

6. 发明申请

US20060267095A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060267095A1
公开(公告)日：2006-11-30
申请号：US11443152
申请日：2006-05-31
申请人： Hideaki Fujiwara
发明人： Hideaki Fujiwara
IPC分类号： H01L27/12
CPC分类号： H01L21/823842
摘要： A semiconductor device capable of reducing deterioration of electron mobility while suppressing depletion of gate electrodes is provided. This semiconductor device includes a metal-containing layer so formed that at least either a first gate electrode or a second gate electrode partially covers a corresponding first or second gate insulating film and a semiconductor layer formed on the metal-containing layer to come into contact with a portion of the corresponding first or second gate insulating film not covered with the metal-containing layer. The first and second gate electrodes contain metals different from each other.
摘要翻译：提供能够减少电子迁移率劣化并抑制栅电极耗尽的半导体器件。该半导体装置包括如此形成的含金属层，使得第一栅极电极或第二栅电极中的至少一个部分地覆盖相应的第一或第二栅极绝缘膜和形成在含金属层上的半导体层以与相应的第一或第二栅绝缘膜的一部分未被含金属层覆盖。第一和第二栅电极包含彼此不同的金属。

7. 发明申请

US20050260818A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050260818A1
公开(公告)日：2005-11-24
申请号：US11132197
申请日：2005-05-19
申请人： Hideaki Fujiwara
发明人： Hideaki Fujiwara
IPC分类号： H01L29/41 , H01L21/336 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L29/66621 , H01L29/4908 , H01L29/66553 , H01L29/66772 , H01L29/78621 , H01L29/78636
摘要： A method for fabricating a semiconductor device includes:isolating a SOI layer on a buried oxide film with a pair of element isolation regions having a perpendicular sidewall; depositing a poly-crystal silicon layer on the isolated SOI layer; implanting a dopant into the poly-crystal silicon layer; depositing a silicon oxide film on the poly-crystal silicon layer; forming a recessed portion by selectively removing the silicon oxide film and the poly-crystal silicon layer in a gate bearing region and then selectively removing the SOI layer in the gate bearing region to a predetermined depth; forming a sidewall spacer on the side wall of the recessed portion; forming source and drain regions by allowing a dopant to diffuse from the poly-crystal silicon layer into the SOI layer; and forming a gate electrode by depositing a gate metal layer after a gate insulating film is formed on the bottom of the recessed portion.
摘要翻译：一种用于制造半导体器件的方法，包括：利用具有垂直侧壁的一对元件隔离区域在掩埋氧化膜上隔离SOI层; 在隔离的SOI层上沉积多晶硅层; 将掺杂剂注入到所述多晶硅层中; 在所述多晶硅层上沉积氧化硅膜; 通过选择性地去除栅极承载区域中的氧化硅膜和多晶硅层，然后选择性地将栅极承载区域中的SOI层去除到预定深度来形成凹陷部分; 在所述凹部的侧壁上形成侧壁间隔物; 通过使掺杂剂从多晶硅层扩散到SOI层中形成源区和漏区; 以及在凹陷部分的底部上形成栅极绝缘膜之后，通过沉积栅极金属层来形成栅电极。

8. 发明授权

US06424002B1 Transistor, transistor array and non-volatile semiconductor memory 失效
标题翻译：晶体管，晶体管阵列和非易失性半导体存储器
公开(公告)号：US06424002B1
公开(公告)日：2002-07-23
申请号：US09063396
申请日：1998-04-21
申请人： Sadao Kondo , Kouichi Yamada , Hideaki Fujiwara
发明人： Sadao Kondo , Kouichi Yamada , Hideaki Fujiwara
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0458 , G11C16/0491 , G11C16/10 , G11C16/16 , G11C16/26 , H01L27/115
摘要： A memory cell in a simple structure having a long life, less variations in the structure and writing characteristic, and a higher operation speed, free from the problem of over-erasure, and permitting down-sizing is disclosed. Floating gate electrodes are arranged on a channel region with a gate insulating film therebetween. A control gate is formed on the floating gate electrodes with a tunnel insulating film therebetween. A central part of the control gate electrode is provided on the channel region to form a select gate. Source/drain regions having the select gate therebetween and the select gate form a select transistor. The coupling capacitance between each of the floating gate electrodes and the control gate electrode is set much larger than the coupling capacitance between each of the floating gate electrodes and the substrate.
摘要翻译：公开了一种具有寿命长，结构变化小，书写特性小的简单结构的存储单元，并且没有过度擦除的问题和允许缩小尺寸的更高的操作速度。浮栅电极布置在其间具有栅绝缘膜的沟道区上。控制栅极形成在浮栅上，其间具有隧道绝缘膜。控制栅电极的中心部分设置在沟道区上以形成选择栅极。具有选择栅极的源极/漏极区域和选择栅极形成选择晶体管。每个浮置栅电极和控制栅电极之间的耦合电容被设置得远大于每个浮栅电极和衬底之间的耦合电容。

9. 发明授权

US5898197A Non-volatile semiconductor memory devices 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5898197A
公开(公告)日：1999-04-27
申请号：US870122
申请日：1997-06-03
申请人： Hideaki Fujiwara
发明人： Hideaki Fujiwara
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/04 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475 , G11C11/5621 , G11C16/0458 , H01L29/42324 , H01L29/66825 , H01L29/7885 , H01L29/7887 , G11C2211/5612
摘要： A non-volatile semiconductor memory device accurately stores multivalued data with reduced damage to an insulating layer. The non-volatile semiconductor memory device includes a floating gate electrode configured to be divided into at least two portions. The first portion is employed for accumulating carriers migrating from at least one control gate electrode through a gate insulating layer to the floating gate electrode.
摘要翻译：非易失性半导体存储器件将绝对层损伤降低的多值数据精确地存储。非易失性半导体存储器件包括被构造为分成至少两部分的浮栅电极。第一部分用于累积从至少一个控制栅极迁移通过栅极绝缘层到载体栅电极的载流子。

10. 发明申请

US20110222210A1 ELECTRODE FOR CAPACITOR AND CAPACITOR 有权
标题翻译：电容器和电容器电极
公开(公告)号：US20110222210A1
公开(公告)日：2011-09-15
申请号：US13129983
申请日：2009-11-17
申请人： Hideaki Fujiwara
发明人： Hideaki Fujiwara
IPC分类号： H01G9/012
CPC分类号： H01G9/052 , H01G9/0032 , H01G9/042 , H01G9/07
摘要： A capacitor includes a positive electrode base material, a dielectric layer, a positive electrode body, a dielectric layer, a negative electrode body, and a negative electrode base material. The positive electrode body is formed on the positive electrode base material and in part is in contact with the positive electrode base material. The positive electrode body is formed by association of a large number of metal particles, and the associated metal particles form a reticular network. The positive electrode base material and the positive electrode body (core part) are formed of a NiTi alloy containing Ni having a large work function. The dielectric layers (high-permittivity insulating film) are formed of titanium oxide. It is preferable that at least one Ni atomic layer is formed at an interface between the high-permittivity insulating film and the core part. Although the Ni atomic layer is preferably formed over the entire interface, the Ni atomic layer may be partially formed at the interface.
摘要翻译：电容器包括正极基材，电介质层，正极体，电介质层，负极体和负极基材。正极体形成在正极基材上，部分与正极基材接触。正极体通过大量金属颗粒的缔合形成，并且相关联的金属颗粒形成网状网络。正极基材和正极体（芯部）由具有大功函数的Ni的NiTi合金形成。电介质层（高电容率绝缘膜）由氧化钛形成。优选在高电容率绝缘膜和芯部之间的界面处形成至少一个Ni原子层。尽管Ni原子层优选在整个界面上形成，但Ni原子层可以部分地形成在界面处。

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