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    • 1. 发明专利
    • Method of manufacturing polarized rare gas
    • 制造极化稀有气体的方法
    • JP2008216136A
    • 2008-09-18
    • JP2007055996
    • 2007-03-06
    • Hideaki Fujiwara英明 藤原
    • FUJIWARA HIDEAKIFUKUTOMI JUNKOIMAI HIROHIKO
    • G01R33/28A61B5/055
    • PROBLEM TO BE SOLVED: To provide a polarized rare gas manufacturing method capable of easily manufacturing rare gas of the high polarization ratio, by restraining reduced polarization.
      SOLUTION: This method manufactures polarized rare gas by irradiating the exciting light into a polarization cell 6 in a magnetic field, by mixing raw material gas including the rare gas and quench gas with alkaline metal vapor by being supplied to the polarization cell 6, and maintains pressure in the polarization cell 6 in 0.05 atmospheric pressure to 0.6 atmospheric pressure when irradiating the exciting light.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 解决的问题:通过抑制极化减小,提供能够容易地制造高极化率的稀有气体的极化稀土气体制造方法。 解决方案:该方法通过将激发光照射到偏振光电池6中,通过将包含稀有气体和骤冷气体的原料气体与碱金属蒸气混合,通过供给到偏振电池6来制造极化稀有气体 并且当照射激发光时,在0.05大气压下将偏振电池6的压力维持为0.6大气压。 版权所有(C)2008,JPO&INPIT
    • 2. 发明申请
    • ELECTRODE FOR CAPACITOR AND CAPACITOR
    • 电容器和电容器电极
    • US20110222210A1
    • 2011-09-15
    • US13129983
    • 2009-11-17
    • Hideaki Fujiwara
    • Hideaki Fujiwara
    • H01G9/012
    • H01G9/052H01G9/0032H01G9/042H01G9/07
    • A capacitor includes a positive electrode base material, a dielectric layer, a positive electrode body, a dielectric layer, a negative electrode body, and a negative electrode base material. The positive electrode body is formed on the positive electrode base material and in part is in contact with the positive electrode base material. The positive electrode body is formed by association of a large number of metal particles, and the associated metal particles form a reticular network. The positive electrode base material and the positive electrode body (core part) are formed of a NiTi alloy containing Ni having a large work function. The dielectric layers (high-permittivity insulating film) are formed of titanium oxide. It is preferable that at least one Ni atomic layer is formed at an interface between the high-permittivity insulating film and the core part. Although the Ni atomic layer is preferably formed over the entire interface, the Ni atomic layer may be partially formed at the interface.
    • 电容器包括正极基材,电介质层,正极体,电介质层,负极体和负极基材。 正极体形成在正极基材上,部分与正极基材接触。 正极体通过大量金属颗粒的缔合形成,并且相关联的金属颗粒形成网状网络。 正极基材和正极体(芯部)由具有大功函数的Ni的NiTi合金形成。 电介质层(高电容率绝缘膜)由氧化钛形成。 优选在高电容率绝缘膜和芯部之间的界面处形成至少一个Ni原子层。 尽管Ni原子层优选在整个界面上形成,但Ni原子层可以部分地形成在界面处。
    • 5. 发明授权
    • Semiconductor memory and semiconductor device
    • 半导体存储器和半导体器件
    • US06897515B2
    • 2005-05-24
    • US09899267
    • 2001-07-06
    • Hideaki Fujiwara
    • Hideaki Fujiwara
    • G11C16/04H01L21/8247H01L27/115H01L29/423H01L29/788H01L29/792
    • H01L27/11521G11C16/0425G11C16/0433H01L29/42336H01L29/7883
    • A semiconductor memory capable of attaining a low voltage, a high-speed operation, low power consumption and a high degree of integration is obtained. This semiconductor memory comprises a floating gate electrode, a first source/drain region having a diode structure employed for controlling the potential of the floating gate electrode and a second source/drain region formed to hold a channel region between the same and the first source/drain region. Thus, when a channel of a transistor is turned on in reading, a large amount of current flows from the first source/drain region having a diode structure to a substrate, whereby high-speed reading can be implemented. Further, a negative voltage is readily applied to the first source/drain region having a diode structure, whereby a low voltage and low power consumption are attained and the scale of a step-up circuit is reduced, and hence a high degree of integration can be attained.
    • 可以获得能够实现低电压,高速运转,低功耗,高集成度的半导体存储器。 该半导体存储器包括浮置栅极电极,具有用于控制浮置栅电极的电位的二极管结构的第一源极/漏极区域和形成为保持其与第一源极/漏极区域之间的沟道区域的第二源极/漏极区域, 漏区。 因此,当晶体管的沟道在读取时导通时,大量的电流从具有二极管结构的第一源极/漏极区流动到衬底,从而可以实现高速读取。 此外,负电压容易地施加到具有二极管结构的第一源/漏区,由此获得低电压和低功耗,并且升压电路的规模减小,因此高集成度 实现。
    • 6. 发明授权
    • Nonvolatile semiconductor memory
    • 非易失性半导体存储器
    • US06642571B2
    • 2003-11-04
    • US10271556
    • 2002-10-17
    • Hideaki Fujiwara
    • Hideaki Fujiwara
    • H01L29788
    • H01L29/66825G11C16/0416G11C16/0425H01L21/28273H01L29/42324
    • A semiconductor memory capable of increasing the coupling ratio between a diffusion layer and a floating gate by reducing the coupling ratio between the floating gate and a control gate thereby easily performing high-speed writing with a low diffusion layer voltage is provided. This semiconductor memory comprises the floating gate, a first diffusion layer capacitively coupled with the floating gate for controlling the potential of the floating gate and the control gate arranged oppositely to the floating gate. In an erase operation, the control gate feeds a tunnel current to the floating gate in a direction substantially parallel to the main surface of a semiconductor substrate. Thus, the tunnel current can be fed by extracting carriers from the floating gate also when the control gate has no region overlapping with the upper portion of the floating gate.
    • 提供一种半导体存储器,其能够通过降低浮动栅极和控制栅极之间的耦合比来增加扩散层和浮置栅极之间的耦合比,从而容易地以低扩散层电压进行高速写入。 该半导体存储器包括浮动栅极,与浮动栅极电容耦合的第一扩散层,用于控制与浮置栅极相对布置的浮置栅极和控制栅极的电位。 在擦除操作中,控制栅极基本上平行于半导体衬底的主表面的方向将浮动栅极提供隧道电流。 因此,当控制栅极没有与浮动栅极的上部重叠的区域时,也可以从浮置栅极提取载流子来馈送隧道电流。
    • 7. 发明授权
    • Method of forming isolation film in semiconductor device
    • 在半导体器件中形成隔离膜的方法
    • US06610581B1
    • 2003-08-26
    • US09584850
    • 2000-06-01
    • Yasuhiro TakedaHideaki Fujiwara
    • Yasuhiro TakedaHideaki Fujiwara
    • H01L218238
    • H01L21/76202H01L21/76205
    • There is disclosed a method of forming an isolation film in a semiconductor device, the method including the steps of: forming a silicon oxide film and a silicon nitride film in that order on a silicon substrate, using a resist pattern as a mask, etching the silicon nitride film and silicon oxide film, and forming trenches in the substrate. In the substrate, the respective trenches form a region in which isolation films are to be formed, and the region between the trenches forms an active region. In this case, each dimension is set so that a ratio W/t of width W to thickness t of the patterned silicon nitride film is 3.8 or more. Subsequently, by removing the resist pattern, subsequently using the silicon nitride film as the mask, and performing thermal oxidation at a temperature of 1050° C. to 1150° C. in an oxygen atmosphere, an isolation film is formed in the trench.
    • 公开了在半导体器件中形成隔离膜的方法,该方法包括以下步骤:在硅衬底上依次形成氧化硅膜和氮化硅膜,使用抗蚀剂图案作为掩模,蚀刻 氮化硅膜和氧化硅膜,并在衬底中形成沟槽。 在衬底中,相应的沟槽形成其中将形成隔离膜的区域,并且沟槽之间的区域形成有源区。 在这种情况下,每个尺寸被设定为使得图案化氮化硅膜的宽度W与厚度t的比W / t为3.8以上。 随后,通过去除抗蚀剂图案,随后使用氮化硅膜作为掩模,并且在氧气氛中在1050℃至1150℃的温度下进行热氧化,在沟槽中形成隔离膜。
    • 9. 发明授权
    • Semiconductor device comprising gate electrode
    • 包括栅电极的半导体器件
    • US07564106B2
    • 2009-07-21
    • US11711726
    • 2007-02-28
    • Hideaki Fujiwara
    • Hideaki Fujiwara
    • H01L29/78
    • H01L21/28079H01L21/28035H01L21/823842H01L21/823857H01L21/823864
    • A semiconductor device capable of reducing a threshold voltage is obtained. The semiconductor device includes a pair of source/drain regions formed on the main surface of a semiconductor region to hold a channel region therebetween, and a gate electrode formed on the channel region through a gate insulating film and including a metal-containing layer arranged in the vicinity of an interface between the gate insulating film and the gate electrode, wherein the metal-containing layer is so formed in the form of dots as to partially cover the surface of the gate insulating film, and the average distance between dots forming the metal-containing layer is set to not more than a diameter of the dot of the metal-containing layer.
    • 获得能够降低阈值电压的半导体器件。 半导体器件包括形成在半导体区域的主表面上以保持其间的沟道区的一对源极/漏极区,以及通过栅极绝缘膜形成在沟道区上的栅极,并且包括含有金属的层 栅极绝缘膜和栅电极之间的界面附近,其中含金属层以点的形式形成为部分地覆盖栅极绝缘膜的表面,并且形成金属的点之间的平均距离 含有层被设定为不大于含金属层的点的直径。
    • 10. 发明申请
    • Semiconductor device
    • 半导体器件
    • US20060267095A1
    • 2006-11-30
    • US11443152
    • 2006-05-31
    • Hideaki Fujiwara
    • Hideaki Fujiwara
    • H01L27/12
    • H01L21/823842
    • A semiconductor device capable of reducing deterioration of electron mobility while suppressing depletion of gate electrodes is provided. This semiconductor device includes a metal-containing layer so formed that at least either a first gate electrode or a second gate electrode partially covers a corresponding first or second gate insulating film and a semiconductor layer formed on the metal-containing layer to come into contact with a portion of the corresponding first or second gate insulating film not covered with the metal-containing layer. The first and second gate electrodes contain metals different from each other.
    • 提供能够减少电子迁移率劣化并抑制栅电极耗尽的半导体器件。 该半导体装置包括如此形成的含金属层,使得第一栅极电极或第二栅电极中的至少一个部分地覆盖相应的第一或第二栅极绝缘膜和形成在含金属层上的半导体层以与 相应的第一或第二栅绝缘膜的一部分未被含金属层覆盖。 第一和第二栅电极包含彼此不同的金属。