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1. 发明授权

US08076720B2 Trench gate type transistor 有权
标题翻译：沟槽型晶体管
公开(公告)号：US08076720B2
公开(公告)日：2011-12-13
申请号：US12447817
申请日：2008-09-26
申请人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
发明人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66734 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/513 , H01L29/66348 , H01L29/7397 , H01L29/7809 , H01L29/7813
摘要： The invention provides a trench gate type transistor in which the gate leakage current is prevented and the gate capacitance is reduced. A trench is formed in an N− type semiconductor layer. A thin silicon oxide film is formed on a region of the N− type semiconductor layer for the active region of the transistor in the trench. On the other hand, a silicon oxide film which is thicker than the silicon oxide film is formed on a region not for the active region. Furthermore, a leading portion extending from inside the trench onto the outside thereof forms a gate electrode contacting the silicon oxide film. This provides a long distance between the gate electrode at the leading portion and the corner portion of the N− type semiconductor layer, thereby preventing the gate leakage current and reducing the gate capacitance.
摘要翻译：本发明提供了一种沟槽栅型晶体管，其中栅极漏电流被防止并且栅极电容减小。在N型半导体层中形成沟槽。在沟槽中的晶体管的有源区域的N型半导体层的区域上形成薄的氧化硅膜。另一方面，在不是有源区的区域上形成比氧化硅膜厚的氧化硅膜。此外，从沟槽内部延伸到其外部的引导部分形成与氧化硅膜接触的栅电极。这提供了在前导部分的栅电极和N-型半导体层的角部之间的长距离，从而防止栅极漏电流并降低栅极电容。

2. 发明授权

US08242557B2 Trench gate type transistor 有权
标题翻译：沟槽型晶体管
公开(公告)号：US08242557B2
公开(公告)日：2012-08-14
申请号：US12447820
申请日：2008-09-26
申请人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
发明人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7809
摘要： The invention provides a trench gate type transistor in which the gate capacitance is reduced, the crystal defect is prevented and the gate breakdown voltage is enhanced. Trenches are formed in an N− type semiconductor layer. A uniformly thick silicon oxide film is formed on the bottom of each of the trenches and near the bottom, being round at corner portions. A silicon oxide film is formed on the upper portion of the sidewall of each of the trenches, which is thinner than the silicon oxide film and round at corner portions. Gate electrodes are formed from inside the trenches onto the outside thereof. The thick silicon oxide film reduces the gate capacitance, and the thin silicon oxide film on the upper portion provides good transistor characteristics. Furthermore, with the round corner portions, the crystal defect does not easily occur, and the gate electric field is dispersed to enhance the gate breakdown voltage.
摘要翻译：本发明提供一种沟槽栅型晶体管，其栅极电容减小，防止了晶体缺陷，提高了栅极击穿电压。沟槽形成在N-型半导体层中。在每个沟槽的底部和底部附近形成均匀厚的氧化硅膜，在角部处是圆形的。在每个沟槽的侧壁的上部形成氧化硅膜，其比氧化硅膜薄并且在角部处圆形。栅极电极从沟槽内部形成到其外部。厚的氧化硅膜减小栅极电容，并且上部的薄氧化硅膜提供良好的晶体管特性。此外，由于圆角部分不容易发生晶体缺陷，并且栅极电场被分散以提高栅极击穿电压。

3. 发明授权

US07998760B2 Manufacture method for photovoltaic module including inspection and repair 有权
标题翻译：光伏组件的制造方法包括检修
公开(公告)号：US07998760B2
公开(公告)日：2011-08-16
申请号：US12728831
申请日：2010-03-22
申请人： Tomonori Tabe
发明人： Tomonori Tabe
IPC分类号： H01L21/66 , H01L21/00
CPC分类号： H01L31/188 , H01L31/0512 , Y02E10/50 , Y10S136/29
摘要： After overlaying a conductive adhesive film and the wiring material on an electrode of a solar cell and temporarily fixing the wiring material to the solar cell by pressure bonding under first temperature/pressurizing condition, the quality of the temporarily fixed solar cell is inspected, a solar cell determined to be defective in the inspection step is removed and the defective solar cell is replaced with a non-defective solar cell. Then, the wiring material is temporarily fixed to the non-defective solar cell by pressure bonding the wiring material with the conductive adhesive film interposed therebetween, under the first temperature/pressurizing condition and the wiring materials are fixed to the solar cell by thermally setting the conductive adhesive film under second temperature condition to apply heat higher than the first temperature condition.
摘要翻译：在将导电性粘合膜和布线材料覆盖在太阳能电池的电极上并在第一温度/加压条件下通过压力接合将布线材料临时固定到太阳能电池上的情况下，检查暂时固定的太阳能电池的质量，在检查步骤中确定为有缺陷的单元被去除，并且用无缺陷的太阳能电池替换有缺陷的太阳能电池。然后，在第一温度/加压条件下，通过将布线材料与导电性粘合膜压接在一起而将布线材料暂时固定到无缺陷的太阳能电池，并且通过热定形来将布线材料固定到太阳能电池导电胶膜在第二温度条件下施加高于第一温度条件的热量。

4. 发明申请

US20100059816A1 TRENCH GATE TYPE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： TRENCH门式晶体管及其制造方法
公开(公告)号：US20100059816A1
公开(公告)日：2010-03-11
申请号：US12447820
申请日：2008-09-26
申请人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
发明人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7809
摘要： The invention provides a trench gate type transistor in which the gate capacitance is reduced, the crystal defect is prevented and the gate breakdown voltage is enhanced. Trenches are formed in an N− type semiconductor layer. A uniformly thick silicon oxide film is formed on the bottom of each of the trenches and near the bottom, being round at corner portions. A silicon oxide film is formed on the upper portion of the sidewall of each of the trenches, which is thinner than the silicon oxide film and round at corner portions. Gate electrodes are formed from inside the trenches onto the outside thereof. The thick silicon oxide film reduces the gate capacitance, and the thin silicon oxide film on the upper portion provides good transistor characteristics. Furthermore, with the round corner portions, the crystal defect does not easily occur, and the gate electric field is dispersed to enhance the gate breakdown voltage.
摘要翻译：本发明提供一种沟槽栅型晶体管，其栅极电容减小，防止了晶体缺陷，提高了栅极击穿电压。沟槽形成在N-型半导体层中。在每个沟槽的底部和底部附近形成均匀厚的氧化硅膜，在角部处是圆形的。在每个沟槽的侧壁的上部形成氧化硅膜，其比氧化硅膜薄并且在角部处圆形。栅极电极从沟槽内部形成到其外部。厚的氧化硅膜减小栅极电容，并且上部的薄氧化硅膜提供良好的晶体管特性。此外，由于圆角部分不容易发生晶体缺陷，并且栅极电场被分散以提高栅极击穿电压。

5. 外观设计

USD694175S1 Solar battery module 有权
标题翻译：太阳能电池模块
公开(公告)号：USD694175S1
公开(公告)日：2013-11-26
申请号：US29379985
申请日：2010-11-29
申请人： Hiroyuki Kannou , Yousuke Ishii , Tomonori Tabe , Yu Maruyama , Kengo Matsune , Koutarou Sumitomo
设计人： Hiroyuki Kannou , Yousuke Ishii , Tomonori Tabe , Yu Maruyama , Kengo Matsune , Koutarou Sumitomo

6. 外观设计

USD670239S1 Solar battery 有权
公开(公告)号：USD670239S1
公开(公告)日：2012-11-06
申请号：US29379989
申请日：2010-11-29
申请人： Hiroyuki Kannou , Yousuke Ishii , Tomonori Tabe , Yu Maruyama , Kengo Matsune , Koutarou Sumitomo
设计人： Hiroyuki Kannou , Yousuke Ishii , Tomonori Tabe , Yu Maruyama , Kengo Matsune , Koutarou Sumitomo

7. 发明申请

US20120125396A1 SOLAR CELL MODULE 有权
标题翻译：太阳能电池模块
公开(公告)号：US20120125396A1
公开(公告)日：2012-05-24
申请号：US13361007
申请日：2012-01-30
申请人： Shigeharu TAIRA , Yukihiro YOSHIMINE , Hiroyuki KANNOU , Tomonori TABE
发明人： Shigeharu TAIRA , Yukihiro YOSHIMINE , Hiroyuki KANNOU , Tomonori TABE
IPC分类号： H01L31/05
CPC分类号： H01L31/022433 , H01L31/0201 , H01L31/02013 , H01L31/022425 , H01L31/022441 , H01L31/05 , H01L31/0504 , H01L31/0516 , Y02E10/50
摘要： In the solar cell module including a plurality of solar cells interconnected with wiring members, each of the solar cells includes a plurality of front-side finger electrodes that are disposed on a light-receiving surface of the solar cell and connected with tabs and a plurality of rear-side finger electrodes that are disposed on a rear surface of the solar cell and connected with tabs. Rear-side auxiliary electrode sections are arranged in regions, which is wider than the front-side finger electrodes, on the rear surface opposite to regions where the front-side finger electrodes are present.
摘要翻译：在太阳能电池模块中，包括与配线部件互连的多个太阳能电池单元，每个太阳能电池包括设置在太阳能电池的受光面并与突片连接的多个前侧手指电极，的后侧指状电极，其设置在太阳能电池的后表面并与突片连接。背面辅助电极部分布置在与前侧手指电极相比较宽的区域中，在与正面指状电极存在的区域相反的背面上。

8. 发明申请

US20100102382A1 TRENCH GATE TYPE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： TRENCH门式晶体管及其制造方法
公开(公告)号：US20100102382A1
公开(公告)日：2010-04-29
申请号：US12447817
申请日：2008-09-26
申请人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
发明人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66734 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/513 , H01L29/66348 , H01L29/7397 , H01L29/7809 , H01L29/7813
摘要： The invention provides a trench gate type transistor in which the gate leakage current is prevented and the gate capacitance is reduced. A trench is formed in an N− type semiconductor layer. A thin silicon oxide film is formed on a region of the N− type semiconductor layer for the active region of the transistor in the trench. On the other hand, a silicon oxide film which is thicker than the silicon oxide film is formed on a region not for the active region. Furthermore, a leading portion extending from inside the trench onto the outside thereof forms a gate electrode contacting the silicon oxide film. This provides a long distance between the gate electrode at the leading portion and the corner portion of the N− type semiconductor layer, thereby preventing the gate leakage current and reducing the gate capacitance.
摘要翻译：本发明提供了一种沟槽栅型晶体管，其中栅极漏电流被防止并且栅极电容减小。在N型半导体层中形成沟槽。在沟槽中的晶体管的有源区域的N型半导体层的区域上形成薄的氧化硅膜。另一方面，在不是有源区的区域上形成比氧化硅膜厚的氧化硅膜。此外，从沟槽内部延伸到其外部的引导部分形成与氧化硅膜接触的栅电极。这提供了在前导部分的栅电极和N-型半导体层的角部之间的长距离，从而防止栅极漏电流并降低栅极电容。

9. 发明授权

US09608138B2 Solar cell module 有权
公开(公告)号：US09608138B2
公开(公告)日：2017-03-28
申请号：US13361007
申请日：2012-01-30
申请人： Shigeharu Taira , Yukihiro Yoshimine , Hiroyuki Kannou , Tomonori Tabe
发明人： Shigeharu Taira , Yukihiro Yoshimine , Hiroyuki Kannou , Tomonori Tabe
IPC分类号： H01L31/00 , H01L31/042 , H02N6/00 , H01L31/0224 , H01L31/02 , H01L31/05
CPC分类号： H01L31/022433 , H01L31/0201 , H01L31/02013 , H01L31/022425 , H01L31/022441 , H01L31/05 , H01L31/0504 , H01L31/0516 , Y02E10/50
摘要： In the solar cell module including a plurality of solar cells interconnected with wiring members, each of the solar cells includes a plurality of front-side finger electrodes that are disposed on a light-receiving surface of the solar cell and connected with tabs and a plurality of rear-side finger electrodes that are disposed on a rear surface of the solar cell and connected with tabs. Rear-side auxiliary electrode sections are arranged in regions, which is wider than the front-side finger electrodes, on the rear surface opposite to regions where the front-side finger electrodes are present.

10. 发明授权

US07655974B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07655974B2
公开(公告)日：2010-02-02
申请号：US11829310
申请日：2007-07-27
申请人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
发明人： Satoru Shimada , Yoshikazu Yamaoka , Kazunori Fujita , Tomonori Tabe
IPC分类号： H01L29/76
CPC分类号： H01L21/761 , H01L21/763 , H01L27/088 , H01L29/1087 , H01L29/41741 , H01L29/41766 , H01L29/66734 , H01L29/7809 , H01L29/7813
摘要： A semiconductor device that reduces the width of an isolation region between semiconductor elements. The semiconductor device includes a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a buried layer formed between the semiconductor substrate and the epitaxial layer, a first trench formed in the epitaxial layer so as to surround the buried layer, and an insulation film formed in the first trench.
摘要翻译：一种半导体器件，其减小半导体元件之间的隔离区域的宽度。半导体器件包括半导体衬底，形成在半导体衬底上的外延层，形成在半导体衬底和外延层之间的掩埋层，形成在外延层中以围绕掩埋层的第一沟槽，以及绝缘膜形成在第一个沟槽。

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