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    • 7. 发明授权
    • Ferroelectric memory and operating method of same
    • 铁电存储器及其操作方法相同
    • US07643325B2
    • 2010-01-05
    • US11896343
    • 2007-08-31
    • Shingo HagiwaraYoshiaki KanekoAmane InoueAkihito KumagaiIsao Fukushi
    • Shingo HagiwaraYoshiaki KanekoAmane InoueAkihito KumagaiIsao Fukushi
    • G11C11/22
    • G11C11/22G11C7/1006
    • A nonvolatile decision memory unit stores decision data indicating whether data stored in the normal memory cells is true or false. An inversion control circuit sets the inverting signal to a valid level with a predetermined probability. A write circuit writes data having logic which is inverse logic of data to be rewritten to the normal memory cells and writes decision data indicating false to the decision memory unit when the inverting signal indicates a valid level. Since inverse data is rewritten at a predetermined frequency, an imprint is prevented when a read operation is executed repetitively. Moreover, since frequent repeating of reverse polarization of the ferroelectric capacitor due to a rewrite operation is prevented, deterioration of the ferroelectric capacitor due to reverse polarization is minimized. Thus, occurrence of the imprint and deterioration of characteristics in the ferroelectric capacitor is prevented, and the reliability of the ferroelectric memory is improved.
    • 非易失性判定存储单元存储指示存储在正常存储单元中的数据是真还是假的判定数据。 反转控制电路以预定的概率将反相信号设置为有效电平。 当反相信号指示有效电平时,写入电路将具有要被重写的数据的反逻辑的逻辑写入正常存储器单元,并将指示为假的判定数据写入判定存储器单元。 由于逆数据以预定频率被重写,所以当重复执行读取操作时,防止压印。 此外,由于防止了由于重写操作而导致的强电介质电容器的反向极化的频繁重复,使得极性反转引起的铁电电容器的劣化最小化。 因此,防止了强电介质电容器的压印的发生和特性的劣化,提高了铁电存储器的可靠性。
    • 8. 发明申请
    • Ferroelectric memory and operating method of same
    • 铁电存储器及其操作方法相同
    • US20080175034A1
    • 2008-07-24
    • US11896343
    • 2007-08-31
    • Shingo HagiwaraYoshiaki KanekoAmane InoueAkihito KumagaiIsao Fukushi
    • Shingo HagiwaraYoshiaki KanekoAmane InoueAkihito KumagaiIsao Fukushi
    • G11C11/22G11C11/24
    • G11C11/22G11C7/1006
    • A nonvolatile decision memory unit stores decision data indicating whether data stored in the normal memory cells is true or false. An inversion control circuit sets the inverting signal to a valid level with a predetermined probability. A write circuit writes data having logic which is inverse logic of data to be rewritten to the normal memory cells and writes decision data indicating false to the decision memory unit when the inverting signal indicates a valid level. Since inverse data is rewritten at a predetermined frequency, an imprint is prevented when a read operation is executed repetitively. Moreover, since frequent repeating of reverse polarization of the ferroelectric capacitor due to a rewrite operation is prevented, deterioration of the ferroelectric capacitor due to reverse polarization is minimized. Thus, occurrence of the imprint and deterioration of characteristics in the ferroelectric capacitor is prevented, and the reliability of the ferroelectric memory is improved.
    • 非易失性判定存储单元存储指示存储在正常存储单元中的数据是真还是假的判定数据。 反转控制电路以预定的概率将反相信号设置为有效电平。 当反相信号指示有效电平时,写入电路将具有要被重写的数据的反逻辑的逻辑写入正常存储器单元,并将指示为假的判定数据写入判定存储器单元。 由于逆数据以预定频率被重写,所以当重复执行读取操作时,防止压印。 此外,由于防止了由于重写操作而导致的强电介质电容器的反向极化的频繁重复,使得极性反转引起的铁电电容器的劣化最小化。 因此,防止了强电介质电容器的压印的发生和特性的劣化,提高了铁电存储器的可靠性。
    • 9. 发明授权
    • ECL to GaAs logic level shift interface circuit
    • ECL到GaAs逻辑电平移位接口电路
    • US5352943A
    • 1994-10-04
    • US13641
    • 1993-02-04
    • Kazuhisa TsukaharaYoshiaki KanekoMaya Koyanagi
    • Kazuhisa TsukaharaYoshiaki KanekoMaya Koyanagi
    • H03K19/0185H03K19/092H03K17/16
    • H03K19/018542
    • A compound semiconductor integrated circuit is adapted to provide an interface with respect to an internal circuit which is driven by first and second power source voltages and operates responsive to a logic signal having a predetermined logic level which is different from an emitter-coupled logic level. The compound semiconductor integrated circuit includes an input circuit part which is driven by the first and third power source voltages and receives an input logic signal having the emitter-coupled logic level, and an output circuit part which is driven by the first and second power source voltages and converts an output signal of the input circuit part into a signal having the predetermined logic level. The second power source voltage is lower than the first power source voltage. The third power source voltage is different from the second power source voltage and is lower than the first power source voltage. The output circuit part supplies an output thereof to the internal circuit.
    • 复合半导体集成电路适于提供相对于由第一和第二电源电压驱动的内部电路的接口,并且响应于具有与发射极耦合逻辑电平不同的预定逻辑电平的逻辑信号来操作。 复合半导体集成电路包括由第一和第三电源电压驱动并接收具有发射极耦合逻辑电平的输入逻辑信号的输入电路部分和由第一和第二电源驱动的输出电路部分 电压并将输入电路部分的输出信号转换成具有预定逻辑电平的信号。 第二电源电压低于第一电源电压。 第三电源电压与第二电源电压不同,低于第一电源电压。 输出电路部分将其输出提供给内部电路。