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1. 发明授权

US07436689B2 Non-volatile semiconductor memory 有权
公开(公告)号：US07436689B2
公开(公告)日：2008-10-14
申请号：US11645537
申请日：2006-12-27
申请人： Isao Fukushi
发明人： Isao Fukushi
IPC分类号： G11C5/06
CPC分类号： G11C11/22 , G11C7/1006 , G11C7/22 , G11C2207/2245
摘要： When an address storing/comparing circuit stores no address identical to an external input address in read operation, in a main memory read data is written back to a data storing area after data read therefrom, and data indicating a sum of a predetermined value and a value of the read data is written to a history storing area after data read therefrom. In a sub memory, after data read from a history storing area, data read from the data storing area of the main memory is written to a data storing area and the data indicating the sum of the predetermined value and the value of the data read from the history storing area of the main memory is written to the history storing area, when the value of the data read from the history storing area of the main memory is larger than that of the sub memory.

2. 发明授权

US4893274A Semiconductor memory device having level converters 失效
标题翻译：具有电平转换器的半导体存储器件
公开(公告)号：US4893274A
公开(公告)日：1990-01-09
申请号：US261298
申请日：1988-10-24
申请人： Isao Fukushi
发明人： Isao Fukushi
IPC分类号： H03K19/0944 , G11C8/06 , G11C11/417 , H03K3/356 , H03K5/00 , H03K19/0185
CPC分类号： G11C8/06 , H03K19/018521 , H03K3/356104
摘要： A semiconductor memory device including a plurality of level converters, each of the level converters including a bridge circuit constituted by four MOS transistors having one type of conductivity, gates of one pair of four transistors opposing each other receiving a first signal and gates of the other pair of four transistors opposing each other receiving a signal complementary to the first signal; a pair of complementary MOS inverter circuits to which a second signal and a signal complementary to the second signal are input, respectively, the outputs of the pair of inverter circuits being connected to a first pair of connecting points positioned alternately in the bridge circuit, respectively; and a flip-flop circuit connected between a second pair of connecting points positioned alternately in the bridge circuit, to thereby output a third signal and a signal complementary to the third signal from the second pair of connecting points, resepctively.

3. 发明授权

US4796233A Bipolar-transistor type semiconductor memory device having redundancy configuration 失效
标题翻译：具有冗余配置的双极晶体管型半导体存储器件
公开(公告)号：US4796233A
公开(公告)日：1989-01-03
申请号：US788587
申请日：1985-10-17
申请人： Tomoharu Awaya , Isao Fukushi
发明人： Tomoharu Awaya , Isao Fukushi
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/84 , G11C29/842
摘要： A bipolar-transistor type semiconductor memory device including a normal memory cell array, redundancy memory cell array, a redundancy driving circuit, and a redundancy address decision circuit. When the redundancy address decision circuit determines that the input address coincides with the address of a defective circuit portion, the redundancy driving circuit is driven to enable the redundancy memory cell array instead of the normal memory cell array.
摘要翻译：包括正常存储单元阵列，冗余存储单元阵列，冗余驱动电路和冗余地址判定电路的双极晶体管型半导体存储器件。当冗余地址判定电路确定输入地址与故障电路部分的地址一致时，驱动冗余驱动电路以使冗余存储单元阵列代替正常存储单元阵列。

4. 发明授权

US08213253B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US08213253B2
公开(公告)日：2012-07-03
申请号：US12696580
申请日：2010-01-29
申请人： Isao Fukushi
发明人： Isao Fukushi
IPC分类号： G11C7/14
CPC分类号： G11C11/22
摘要： A regular capacitor is saturated by an electric charge of a regular memory cell holding a high logic level and is not saturated by an electric charge from the regular memory cell holding a low logic level. A reference capacitor is saturated by the electric charge from a reference memory cell holding the high logic level. A differential sense amplifier differentially amplifies a difference between a regular read voltage read from the regular capacitor and a voltage which is lower by a first voltage than a reference read voltage being a saturation voltage read from the reference capacitor, and generates logic of data held in the memory cell. Accordingly, a difference between the reference voltage and the read voltage corresponding to the low logic level can be made relatively large. As a result, it is possible to improve a read margin.
摘要翻译：常规电容器由保持高逻辑电平的常规存储单元的电荷饱和，并且不被来自保持低逻辑电平的常规存储单元的电荷饱和。参考电容器由保持高逻辑电平的参考存储单元的电荷饱和。差分读出放大器差分放大从常规电容器读取的常规读取电压与低于作为从参考电容器读取的饱和电压的参考读取电压的第一电压的电压之间的差值，并产生保持在存储单元。因此，可以使参考电压与对应于低逻辑电平的读取电压之间的差相对较大。结果，可以提高读取余量。

5. 发明申请

US20100128515A1 SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器
公开(公告)号：US20100128515A1
公开(公告)日：2010-05-27
申请号：US12696580
申请日：2010-01-29
申请人： Isao Fukushi
发明人： Isao Fukushi
IPC分类号： G11C11/24 , G11C7/02 , G11C5/14 , G11C7/00
CPC分类号： G11C11/22
摘要： A regular capacitor is saturated by an electric charge of a regular memory cell holding a high logic level and is not saturated by an electric charge from the regular memory cell holding a low logic level. A reference capacitor is saturated by the electric charge from a reference memory cell holding the high logic level. A differential sense amplifier differentially amplifies a difference between a regular read voltage read from the regular capacitor and a voltage which is lower by a first voltage than a reference read voltage being a saturation voltage read from the reference capacitor, and generates logic of data held in the memory cell. Accordingly, a difference between the reference voltage and the read voltage corresponding to the low logic level can be made relatively large. As a result, it is possible to improve a read margin.
摘要翻译：常规电容器由保持高逻辑电平的常规存储单元的电荷饱和，并且不被来自保持低逻辑电平的常规存储单元的电荷饱和。参考电容器由保持高逻辑电平的参考存储单元的电荷饱和。差分读出放大器差分放大从常规电容器读取的常规读取电压与低于作为从参考电容器读取的饱和电压的参考读取电压的第一电压的电压之间的差值，并产生保持在存储单元。因此，可以使参考电压与对应于低逻辑电平的读取电压之间的差相对较大。结果，可以提高读取余量。

6. 发明申请

US20080043512A1 Non-volatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20080043512A1
公开(公告)日：2008-02-21
申请号：US11645537
申请日：2006-12-27
申请人： Isao Fukushi
发明人： Isao Fukushi
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/1006 , G11C7/22 , G11C2207/2245
摘要： When an address storing/comparing circuit stores no address identical to an external input address in read operation, in a main memory read data is written back to a data storing area after data read therefrom, and data indicating a sum of a predetermined value and a value of the read data is written to a history storing area after data read therefrom. In a sub memory, after data read from a history storing area, data read from the data storing area of the main memory is written to a data storing area and the data indicating the sum of the predetermined value and the value of the data read from the history storing area of the main memory is written to the history storing area, when the value of the data read from the history storing area of the main memory is larger than that of the sub memory.
摘要翻译：当地址存储/比较电路在读取操作中不存储与外部输入地址相同的地址时，在主存储器中，从数据读出数据之后，读取数据被写回到数据存储区域，并且指示预定值和读取数据的值在从其读取数据之后被写入历史存储区域。在子存储器中，在从历史存储区域读取数据之后，从主存储器的数据存储区域读取的数据被写入数据存储区域，并且指示预定值和读取的数据值之和的数据当从主存储器的历史存储区读取的数据的值大于子存储器的历史存储区域的值时，将主存储器的历史存储区域写入历史存储区域。

7. 发明申请

US20060146590A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20060146590A1
公开(公告)日：2006-07-06
申请号：US11134332
申请日：2005-05-23
申请人： Isao Fukushi , Shoichiro Kawashima
发明人： Isao Fukushi , Shoichiro Kawashima
IPC分类号： G11C11/22
CPC分类号： H01L27/11507 , G11C11/22 , H01L27/11502
摘要： A ferroelectric memory has a plurality of memory cells respectively having a cell transistor and ferroelectric capacitor whose one terminal is connected with the cell transistor, a plurality of word lines respectively connected with said cell transistor, a plurality of plate lines connected with the other terminal of said ferroelectric capacitor and intersecting with said word lines, a plurality of local bit lines connected with said cell transistors, and a global bit line that is selectively connected with local bit lines. Furthermore, the ferroelectric memory has a sensing amplifier unit that detects the amount of charging of the local bit lines from said memory cells while maintaining the potential of the local bit lines at a potential equivalent to the non-selected plate lines, during reading.
摘要翻译：铁电存储器具有分别具有一个端子与单元晶体管连接的单元晶体管和铁电电容器的多个存储单元，分别与所述单元晶体管连接的多个字线，与另一个端子连接的多个板线所述铁电电容器与所述字线相交，与所述单元晶体管连接的多个局部位线以及与局部位线选择性连接的全局位线。此外，铁电存储器具有感测放大器单元，其在读取期间检测来自所述存储单元的局部位线的充电量，同时将局部位线的电位保持在与未选择的板线相当的电位。

8. 发明授权

US06836426B1 Semiconductor memory device with proper sensing timing 有权
标题翻译：具有适当感应定时的半导体存储器件
公开(公告)号：US06836426B1
公开(公告)日：2004-12-28
申请号：US10786333
申请日：2004-02-26
申请人： Isao Fukushi , Shoichiro Kawashima
发明人： Isao Fukushi , Shoichiro Kawashima
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C7/06 , G11C7/065 , G11C2207/065
摘要： A semiconductor memory device includes a memory cell, a signal line on which a potential responsive to data read from the memory cell appears, a potential detecting circuit which outputs a detection signal in response to detecting that the potential on the signal line exceeds a predetermined potential, and a sense amplifier which starts amplifying the potential on the signal line in response to the detection signal.
摘要翻译：半导体存储器件包括存储单元，响应于从存储单元读取的数据的电位出现的信号线，响应于检测到信号线上的电位超过预定电位而输出检测信号的电位检测电路以及响应于检测信号开始放大信号线上的电位的读出放大器。

9. 发明授权

US4757474A Semiconductor memory device having redundancy circuit portion 失效
标题翻译：具有冗余电路部分的半导体存储器件
公开(公告)号：US4757474A
公开(公告)日：1988-07-12
申请号：US11268
申请日：1987-01-21
申请人： Isao Fukushi , Yasuhiko Maki
发明人： Isao Fukushi , Yasuhiko Maki
IPC分类号： G11C29/00 , G11C11/40
CPC分类号： G11C29/806
摘要： A semiconductor memory device includes a redundancy circuit having upper address bit input terminals receiving upper address bit, lower address bit input terminals receiving lower address bits, a regular memory cell array having a plurality of word lines and bit lines, and a plurality of memory cells are arranged at each intersection of the word and bit lines. A redundancy memory cell array is provided having a plurality of word and bit lines, and a plurality of memory cells are arranged at each intersection of the word and bit lines. The capacity of the redundancy memory cell array being smaller than the regular memory cell array. A first selection circuit selects a word or bit line in the regular memory cell array in accordance with the upper and lower address bits. A second selection circuit select a word or bit line in the redundancy memory cell array in accordance with the lower address bits. A redundancy address programming circuit programs the upper address bits corresponding to defective memory cells in the regular memory cell array. A control circuit compares the input upper address bits with the programmed upper address bits and controls the first and second selection circuits to inhibit the selection of the word or bit lines in the regular memory cell array. A predetermined word or bit line in the redundancy memory cell array is selected therefor when each of the input upper address bits coincides with each of the programmed upper address bits.

10. 发明授权

US07688121B2 Power supply voltage detection circuit 有权
标题翻译：电源电压检测电路
公开(公告)号：US07688121B2
公开(公告)日：2010-03-30
申请号：US11362151
申请日：2006-02-27
申请人： Mitsuhiro Ogai , Isao Fukushi
发明人： Mitsuhiro Ogai , Isao Fukushi
IPC分类号： H02H3/24
CPC分类号： H03K17/223
摘要： A power supply voltage detection circuit is provided including: a first switch to connect between a power supply voltage terminal and a first terminal according to a power supply voltage detection signal and an external signal; a second switch to connect between a reference potential terminal and a second terminal according to the power supply voltage detection signal and the external signal; a first resistance connected between the second terminal and the power supply voltage terminal; and a third switch connecting between the first terminal and the reference potential terminal according to a voltage of the second terminal; and an output circuit outputting the power supply voltage detection signal based on a signal from the first terminal.
摘要翻译：提供一种电源电压检测电路，包括：第一开关，根据电源电压检测信号和外部信号连接电源电压端子和第一端子; 第二开关，根据电源电压检测信号和外部信号，在基准电位端子与第二端子之间连接; 连接在第二端子和电源电压端子之间的第一电阻; 以及第三开关，其根据所述第二端子的电压连接在所述第一端子和所述参考电位端子之间; 以及输出电路，其基于来自第一端子的信号输出电源电压检测信号。

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