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1. 发明申请

US20130099823A1 OUTPUT DRIVER, DEVICES HAVING THE SAME, AND GROUND TERMINATION 有权
标题翻译：输出驱动器，具有相同功能的设备和接地终端
公开(公告)号：US20130099823A1
公开(公告)日：2013-04-25
申请号：US13659543
申请日：2012-10-24
申请人： David MOON , Yong Cheol BAE , Min Su AHN , Young Jin JEON
发明人： David MOON , Yong Cheol BAE , Min Su AHN , Young Jin JEON
IPC分类号： H03K19/0185
CPC分类号： H04L25/028 , H03K19/018521 , H03K19/01855 , H04L25/0292
摘要： An integrated circuit comprising an output driver including an output terminal, and a receiving circuit including a termination resistor connected between the output terminal and a ground. The output driver comprising a first NMOS transistor configured to pull up a voltage of the output terminal to a pull-up voltage in response to a pull-up signal, and a second NMOS transistor configured to pull down the output terminal to a ground voltage in response to a pull-down signal.
摘要翻译：一种集成电路，包括：输出驱动器，包括输出端子;以及接收电路，包括连接在输出端子和地之间的终端电阻器。输出驱动器包括第一NMOS晶体管，其被配置为响应于上拉信号将输出端子的电压上拉至上拉电压;以及第二NMOS晶体管，被配置为将输出端子下拉到地电压响应下拉信号。

2. 发明授权

US06373754B1 Semiconductor memory device having stable internal supply voltage driver 有权
标题翻译：具有稳定的内部电源电压驱动器的半导体存储器件
公开(公告)号：US06373754B1
公开(公告)日：2002-04-16
申请号：US09617208
申请日：2000-07-17
申请人： Yong-cheol Bae , Gi-hong Kim
发明人： Yong-cheol Bae , Gi-hong Kim
IPC分类号： G11C700
CPC分类号： G11C5/147
摘要： A semiconductor memory device, in which the output of an internal supply voltage is stable, is provided. The semiconductor memory device includes a memory cell array block, a differential amplifier, using a reference voltage and an internal supply voltage fed back from the memory cell array block as inputs, an internal supply voltage driver for supplying an internal supply voltage to the memory cell array block in response to the output of the differential amplifier, a pull down circuit for pulling down the output port of the differential amplifier in response to a control signal having a predetermined pulse, and a control signal generating circuit for generating the control signal.
摘要翻译：提供了其中内部电源电压的输出稳定的半导体存储器件。半导体存储器件包括存储单元阵列块，差分放大器，使用参考电压和从存储单元阵列块反馈的内部电源电压作为输入;内部电源电压驱动器，用于向存储单元提供内部电源电压响应于所述差分放大器的输出，用于响应于具有预定脉冲的控制信号来下拉所述差分放大器的输出端口的下拉电路，以及用于产生所述控制信号的控制信号发生电路。

3. 发明授权

US06192429B1 Memory device having a controller capable of disabling data input/output mask (DQM) input buffer during portions of a read operation and a write operation 失效
标题翻译：具有能够在读取操作和写入操作的部分期间禁用数据输入/输出掩码（DQM）输入缓冲器的控制器的存储器件
公开(公告)号：US06192429B1
公开(公告)日：2001-02-20
申请号：US09103078
申请日：1998-06-23
申请人： Woo-seop Jeong , Yong-cheol Bae
发明人： Woo-seop Jeong , Yong-cheol Bae
IPC分类号： G11C706
CPC分类号： G11C7/1087 , G11C7/1006 , G11C7/1078
摘要： An integrated circuit memory device includes a DQM input buffer controller that enables the DQM buffer to process the DQM mask signal during a row active period of a read operation and a write operation of an integrated circuit memory device, and during a latency period of the read operation and the write operation, and that disables the DQM buffer otherwise during the read operation and the write operation. Thus, the DQM buffer is enabled to process the DQM mask signal during those portions of the read and write operations in which the external DQM mask signal is received and the DQM buffer is otherwise disabled during the read and write operations. The controller can also disable the DQM buffer during a refresh operation of the memory device and a power-down operation of the memory device. Accordingly, reduced current consumption in the DQM buffers may be obtained by only enabling the DQM input buffers when a DQM mask signal is expected during the read and write operations of the memory device.
摘要翻译：集成电路存储器件包括DQM输入缓冲器控制器，其使DQM缓冲器能够在读操作的行活动期和集成电路存储器件的写操作期间以及在读取的等待时间期间处理DQM屏蔽信号操作和写入操作，否则在读取操作和写入操作期间禁用DQM缓冲区。因此，DQM缓冲器能够在接收外部DQM屏蔽信号的读取和写入操作的那些部分期间处理DQM屏蔽信号，并且在读取和写入操作期间禁用DQM缓冲器。控制器还可以在存储器件的刷新操作和存储器件的掉电操作期间禁用DQM缓冲器。因此，可以通过在存储器件的读取和写入操作期间期望DQM掩模信号时仅使能DQM输入缓冲器来获得DQM缓冲器中的减少的电流消耗。

4. 发明授权

US09105317B2 Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device 有权
标题翻译：能够校准半导体存储器件的输出电压电平的存储器系统和校准半导体存储器件的输出电压电平的方法
公开(公告)号：US09105317B2
公开(公告)日：2015-08-11
申请号：US13611867
申请日：2012-09-12
申请人： Yoon-Joo Eom , Young-Jin Jeon , Yong-Cheol Bae , Young-Chul Cho
发明人： Yoon-Joo Eom , Young-Jin Jeon , Yong-Cheol Bae , Young-Chul Cho
IPC分类号： H03K19/003 , G11C7/10 , H03K19/00 , G11C29/02
CPC分类号： G11C7/1057 , G11C29/021 , G11C29/028 , G11C2207/2254 , H03K19/0005
摘要： Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.
摘要翻译：提供了一种半导体存储器件和包括该半导体存储器件的存储器系统，其可以考虑到沟道环境和存储器控制器的管芯端接（ODT）电阻的不匹配来校准输出电压的电平。存储器系统包括存储器控制器和半导体存储器件。半导体存储器件被配置为基于存储器控制器的驱动信息生成参考电压，并且当半导体存储器件电连接到存储器控制器时，基于参考电压校准输出电压电平。

5. 发明授权

US6079023A Multi-bank memory devices having common standby voltage generator for powering a plurality of memory array banks in response to memory array bank enable signals 有权
标题翻译：具有用于响应于存储器阵列组使能信号为多个存储器阵列组供电的共同备用电压发生器的多存储体存储器件
公开(公告)号：US6079023A
公开(公告)日：2000-06-20
申请号：US222853
申请日：1998-12-30
申请人： Sei-Seung Yoon , Yong-Cheol Bae
发明人： Sei-Seung Yoon , Yong-Cheol Bae
IPC分类号： G11C11/413 , G11C5/14 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/4193 , G06F1/30
CPC分类号： G11C8/12 , G11C5/14
摘要： A semiconductor memory device having a plurality of memory array banks, a plurality of active array voltage generators, a standby array voltage generator and a plurality of switching means is provided. The semiconductor memory device includes a plurality of memory array banks in which information is stored, a plurality of active array voltage generators connected to the memory array banks, for generating predetermined active voltages in response to memory array bank enable signals for activating the memory array banks, a standby array voltage generator for generating a predetermined standby voltage so that the memory array banks are maintained in a standby state for operation, and a plurality of switching means connected between the memory array banks and the standby array voltage generator, for disconnecting the output of the standby array voltage generator from memory array banks in response to memory array bank enable signals for activating the memory array banks. The power consumption of the semiconductor memory device is reduced.
摘要翻译：提供具有多个存储器阵列组，多个有源阵列电压发生器，备用阵列电压发生器和多个开关装置的半导体存储器件。半导体存储器件包括存储有信息的多个存储器阵列组，连接到存储器阵列组的多个有源阵列电压发生器，用于响应用于激活存储器阵列组的存储器阵列组使能信号而产生预定有效电压备用阵列电压发生器，用于产生预定的待机电压，使得存储器阵列组保持在待机状态以用于操作;以及多个开关装置，连接在存储器阵列组和备用阵列电压发生器之间，用于断开输出响应于用于激活存储器阵列组的存储器阵列组使能信号，来自存储器阵列组的备用阵列电压发生器。半导体存储器件的功耗降低。

6. 发明授权

US5796293A Voltage boosting circuits having backup voltage boosting capability 失效
标题翻译：具有备用升压能力的升压电路
公开(公告)号：US5796293A
公开(公告)日：1998-08-18
申请号：US748189
申请日：1996-11-12
申请人： Sei-Seung Yoon , Yong-Cheol Bae
发明人： Sei-Seung Yoon , Yong-Cheol Bae
IPC分类号： G11C11/413 , G11C5/14 , G11C8/08 , G11C11/407 , H01L21/8242 , H01L27/108 , H02M3/07 , G05F1/10
CPC分类号： G11C5/145 , G11C8/08
摘要： Voltage boosting circuits include backup voltage boosting circuits which are enabled during high current loading conditions when voltage sags in the potential of a boosted signal line(s) are encountered, and which provide independent level detection capability to bypass main voltage level detectors when relatively severe voltage sags are anticipated. In particular, voltage boosting circuits are provided which contain a main voltage boosting circuit and a backup voltage boosting circuit therein. The main voltage boosting circuit is typically powered at a first reference potential (e.g., Vcc) and preferably contains a main level detector, a built-in oscillator and a main pump coupled in series to drive a signal line (e.g., Vpp) to a boosted reference potential which is greater than the first reference potential, if a potential of the signal line drops below a second reference potential. To supplement the voltage boosting capability of the main pump, a backup voltage boosting circuit is provided containing an independent voltage level detector and at least one backup pump coupled in series therewith, to drive the signal line to the boosted reference potential, if the potential of the signal line drops below a third reference potential which may be greater than or equal to the second reference potential. Accordingly, the occurrence of relatively small voltage sags in the potential of the boosted signal line (e.g., Vpp) can trigger the backup pump during anticipated high current loading conditions, while the occurrence of larger voltage sags in the potential can trigger the main pump to assist the backup pump.
摘要翻译：升压电路包括备用升压电路，其在高电流负载状态期间能够在遇到升压信号线的电位的电压骤降时使能，并且当相对严重的电压时提供独立的电平检测能力来旁路主电压电平检测器预计会下滑。特别地，提供了在其中包含主升压电路和备用升压电路的升压电路。主升压电路通常以第一参考电位（例如，Vcc）供电，并且优选地包含主电平检测器，内置振荡器和串联耦合的主泵，以将信号线（例如Vpp）驱动到如果信号线的电位低于第二参考电位，则升高参考电位大于第一参考电位。为了补充主泵的升压能力，提供备用升压电路，其包含独立的电压电平检测器和与串联耦合的至少一个备用泵，以将信号线驱动到升压的参考电位，如果电压信号线下降到可能大于或等于第二参考电位的第三参考电位以下。因此，在预期的高电流负载条件期间，升压信号线的电位（例如，Vpp）中的相对小的电压下降的发生可以触发备用泵，而在电位中较大的电压下降的发生可以触发主泵协助备用泵。

7. 发明授权

US08928349B2 On-die termination circuit, semiconductor memory device and memory system 有权
标题翻译：片上终端电路，半导体存储器件和存储器系统
公开(公告)号：US08928349B2
公开(公告)日：2015-01-06
申请号：US13755418
申请日：2013-01-31
申请人： Ki-Seok Oh , Joon-Young Park , Yong-Hun Ahn , Yong-Cheol Bae , Yong-Gwon Jeong , Jong-Hyun Choi
发明人： Ki-Seok Oh , Joon-Young Park , Yong-Hun Ahn , Yong-Cheol Bae , Yong-Gwon Jeong , Jong-Hyun Choi
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0175 , H04L25/02 , G11C7/10
CPC分类号： H03K19/017545 , G11C7/1057 , G11C2207/2272 , H03K19/0175 , H04L25/0264
摘要： An ODT circuit is activated/deactivated in response to a latency control signal or a clock enable signal. The ODT circuit includes an ODT control circuit and an ODT section. The ODT control circuit determines an ODT status based on a read latency control signal (RL) and/or a write latency control signal (WL) to generate an ODT control signal. The ODT section is activated/deactivated in response to the ODT control signal.
摘要翻译：响应延迟控制信号或时钟使能信号，ODT电路被激活/去激活。 ODT电路包括ODT控制电路和ODT部分。 ODT控制电路基于读等待时间控制信号（RL）和/或写等待时间控制信号（WL）来确定ODT状态，以产生ODT控制信号。响应于ODT控制信号，ODT部分被激活/去激活。

8. 发明申请

US20140028345A1 ON-DIE TERMINATION CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM 有权
标题翻译： ON-DIE终止电路，半导体存储器件和存储器系统
公开(公告)号：US20140028345A1
公开(公告)日：2014-01-30
申请号：US13755418
申请日：2013-01-31
申请人： KI-SEOK OH , JOON-YOUNG PARK , YONG-HUN AHN , YONG-CHEOL BAE , YONG-GWON JEONG , JONG-HYUN CHOI
发明人： KI-SEOK OH , JOON-YOUNG PARK , YONG-HUN AHN , YONG-CHEOL BAE , YONG-GWON JEONG , JONG-HYUN CHOI
IPC分类号： H03K19/0175
CPC分类号： H03K19/017545 , G11C7/1057 , G11C2207/2272 , H03K19/0175 , H04L25/0264
摘要： An ODT circuit is activated/deactivated in response to a latency control signal or a clock enable signal. The ODT circuit includes an ODT control circuit and an ODT section. The ODT control circuit determines an ODT status based on a read latency control signal (RL) and/or a write latency control signal (WL) to generate an ODT control signal. The ODT section is activated/deactivated in response to the ODT control signal.
摘要翻译：响应延迟控制信号或时钟使能信号，ODT电路被激活/去激活。 ODT电路包括ODT控制电路和ODT部分。 ODT控制电路基于读等待时间控制信号（RL）和/或写等待时间控制信号（WL）来确定ODT状态，以产生ODT控制信号。响应于ODT控制信号，ODT部分被激活/去激活。

9. 发明申请

US20130201765A1 POWER MIXING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：功率混合电路和包括其的半导体存储器件
公开(公告)号：US20130201765A1
公开(公告)日：2013-08-08
申请号：US13619793
申请日：2012-09-14
申请人： Young-Chul Cho , Young-Jin Jeon , Yong-Cheol Bae
发明人： Young-Chul Cho , Young-Jin Jeon , Yong-Cheol Bae
IPC分类号： G11C5/14 , G11C7/10 , G06G7/12
CPC分类号： G11C5/147 , G11C5/04 , G11C5/148 , G11C7/02 , G11C7/1012 , G11C7/1057 , G11C7/20
摘要： A power mixing circuit capable of maintaining a stable output voltage in a deep-power- down mode is provided. The power mixing circuit includes an input buffer, a power mixing control circuit, a power mixing driver and an output buffer. The input buffer is configured to operate using a first supply voltage, and to generate a first voltage signal in response to an input signal. The power mixing control circuit is configured to generate a power mixing control signal based on a power-up signal and a deep-power-down mode signal. The power mixing driver is configured to operate using an external supply voltage and a second supply voltage, to perform power mixing on the external supply voltage and the second supply voltage, and to generate a second voltage signal. The output buffer is configured to operate using the second supply voltage, and to generate an output signal.
摘要翻译：提供了能够在深度断电模式下保持稳定的输出电压的功率混合电路。功率混合电路包括输入缓冲器，功率混合控制电路，功率混合驱动器和输出缓冲器。输入缓冲器被配置为使用第一电源电压进行操作，并且响应于输入信号产生第一电压信号。功率混合控制电路被配置为基于上电信号和深度掉电模式信号来产生功率混合控制信号。功率混合驱动器被配置为使用外部电源电压和第二电源电压进行操作，以对外部电源电压和第二电源电压进行功率混合，并产生第二电压信号。输出缓冲器被配置为使用第二电源电压进行操作，并且产生输出信号。

10. 发明授权

US06343040B2 Auto precharge control signal generating circuits for semiconductor memory devices and auto precharge control methods 有权
标题翻译：用于半导体存储器件的自动预充电控制信号发生电路和自动预充电控制方法
公开(公告)号：US06343040B2
公开(公告)日：2002-01-29
申请号：US09792421
申请日：2001-02-23
申请人： Yong Cheol Bae
发明人： Yong Cheol Bae
IPC分类号： G11C700
CPC分类号： G11C7/22
摘要： An auto precharge control signal generating circuit includes an output enable circuit that is reset in response to a precharge operation and generates an output enable signal by latching an auto precharge command signal. A delay circuit also is provided which generates a 1 clock delay signal by delaying an active period of a column bank address signal by 1 clock, and generates a 1 clock delay signal having an active period including a non-active period sufficiently between a previous column bank address signal and a present column bank address signal in case that the burst length is 1. A combining circuit generates an auto precharge control signal by combining the column bank address signal and the 1 clock delay signal in response to the output enable signal, in order to perform the auto precharge operation after delaying 2 clock from the last data input in response to a continued auto precharge burst write command. Therefore, when the burst length is 1 in case that the time from the last data input to the auto precharge is 2 clock cycles in burst write, the present invention prevents the generation of unnecessary auto precharge control signal resulting from the crossing of the 1 clock delay signal and the column bank address signal in the middle of continuous burst write operation.
摘要翻译：自动预充电控制信号产生电路包括一个响应于预充电操作复位的输出使能电路，并通过锁存自动预充电命令信号产生一个输出使能信号。还提供延迟电路，其通过将列组地址信号的有效周期延迟1个时钟来产生1个时钟延迟信号，并且产生具有充分的活动周期的1个时钟延迟信号，该有效周期包括前一列银行地址信号和当前的列存储体地址信号，在突发长度为1的情况下。组合电路通过响应于输出使能信号组合列组地址信号和1个时钟延迟信号来产生自动预充电控制信号，响应于继续的自动预充电突发写入命令，从最后的数据输入延迟2个时钟之后执行自动预充电操作。因此，在从上一次数据输入到自动预充电的时间在突发写入中为2个时钟周期的情况下，当突发长度为1时，本发明防止产生由1个时钟的交叉引起的不必要的自动预充电控制信号延迟信号和列组地址信号在连续脉冲串写入操作的中间。

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