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1. 发明授权

US5023476A Semiconductor device with power supply mode-change controller for reliability testing 失效
标题翻译：具有电源模式变换控制器的半导体器件，用于可靠性测试
公开(公告)号：US5023476A
公开(公告)日：1991-06-11
申请号：US299424
申请日：1989-01-23
申请人： Yohji Watanabe , Tohru Furuyama
发明人： Yohji Watanabe , Tohru Furuyama
IPC分类号： H01L21/66 , G05F1/46 , G06F1/04 , G11C5/14 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , H01L21/822 , H01L27/04
CPC分类号： G11C5/147 , G05F1/465 , H01L2924/0002
摘要： An integrated semiconductor device is disclosed which has a highly-integrated circuit formed on a substrate. A constant voltage generator is connected to the integrated circuit, for receiving an externally-supplied d.c. power supply voltage to produce a regulated d.c. voltage, the potential level of which is lower than the external power supply voltage and remains substantially constant irrespective of the external power supply voltage. A mode-change controller is connected in parallel with the voltage generator, for supplying the output d.c. voltage of the voltage generator to the integrated circuit as an internal power supply voltage in a normal operation mode. When the device is subjected to an accelerated test using an increased power supply voltage, a switching transistor is rendered conductive under the control of a control circuit, thereby allowing the external power supply voltage to be directly applied to the integrated circuit.

2. 发明授权

US4967395A Dram with (1/2)VCC precharge and selectively operable limiting circuit 失效
标题翻译：具有（1/2）VCC预充电和选择性操作的限制电路
公开(公告)号：US4967395A
公开(公告)日：1990-10-30
申请号：US304173
申请日：1989-01-31
申请人： Yohji Watanabe , Tohru Furuyama
发明人： Yohji Watanabe , Tohru Furuyama
IPC分类号： G11C11/409 , G11C11/4074 , G11C11/4076 , G11C11/4094
CPC分类号： G11C11/4076 , G11C11/4074 , G11C11/4094
摘要： An amplitude limiting circuit is arranged in a DRAM with (1/2) VCC precharge to equalize an amplitude between a precharge voltage and an "H" level output of each pair of bit lines charged and discharged in an active cycle with an amplitude of the precharge voltage and an "L" level output of each pair of bit lines.
摘要翻译：幅度限制电路被布置在具有（1/2）VCC预充电的DRAM中，以使得在活动周期中充电和放电的每对位线的预充电电压和“H”电平输出之间的幅度相等，每对位线的预充电电压和“L”电平输出。

3. 发明授权

US4833341A Semiconductor device with power supply voltage converter circuit 失效
标题翻译：具有电源电压转换器电路的半导体器件
公开(公告)号：US4833341A
公开(公告)日：1989-05-23
申请号：US31263
申请日：1987-03-30
申请人： Yohji Watanabe , Tohru Furuyama
发明人： Yohji Watanabe , Tohru Furuyama
IPC分类号： H01L21/66 , G05F1/46 , G06F1/04 , G11C5/14 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , H01L21/822 , H01L27/04
CPC分类号： G11C5/147 , G05F1/465 , H01L2924/0002
摘要： An integrated semiconductor device is disclosed which has a highly-integrated circuit formed on a substrate. A constant voltage generator is connected to the integrated circuit, for receiving an externally-supplied d.c. power supply voltage to produce a regulated d.c. voltage, the potential level of which is lower than the external power supply voltage and remains substantially constant irrespective of the external power supply voltage. A mode-change controller is connected in parallel with the voltage generator, for supplying the output d.c. voltage of the voltage generator to the integrated circuit as an internal power supply voltage in a normal operation mode. When the device is subjected to an accelerated test using an increased power supply voltage, a switching transistor is rendered conductive under the control of a control circuit, thereby allowing the external power supply voltage to be directly applied to the integrated circuit.
摘要翻译：公开了一种集成半导体器件，其具有形成在衬底上的高度集成电路。恒压发生器连接到集成电路，用于接收外部提供的直流电。电源电压产生调节直流。电压，其电位电平低于外部电源电压，并且与外部电源电压无关地保持大致恒定。模式变化控制器与电压发生器并联连接，用于提供输出直流。电压发生器的电压作为正常工作模式下的内部电源电压。当使用增加的电源电压对器件进行加速测试时，在控制电路的控制下使开关晶体管导通，从而允许外部电源电压直接施加到集成电路。

4. 发明授权

US5532963A Semiconductor memory and screening test method thereof 失效
标题翻译：半导体存储器及其筛选试验方法
公开(公告)号：US5532963A
公开(公告)日：1996-07-02
申请号：US523741
申请日：1995-09-05
申请人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
发明人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
IPC分类号： G11C29/02 , G11C29/24 , G11C29/50 , G11C7/00
CPC分类号： G11C29/025 , G11C29/02 , G11C29/028 , G11C29/24 , G11C29/50 , G11C11/401 , G11C2029/5004 , G11C2029/5006
摘要： A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.
摘要翻译：半导体存储器包括动态型存储单元阵列，其布置成形成矩阵并且设置有通常连接到相应列的存储器单元的字线和共同连接到各行的存储单元的位线的虚拟单元部分，虚拟单元部分具有第一组虚拟通过相应的第一电容连接到所述存储单元阵列的相应互补位线对的字线和通过相应的第二电容连接到所述存储单元阵列的相应互补位线对的第二组虚拟字线，线电势控制电路，当所述存储单元阵列的所述字线被激活时，能够可选地控制驱动所选择的虚拟字线的模式，以及连接到所述存储单元阵列的相应互补位线对的读出放大器，用于从所选存储单元读取数据的存储单元阵列到相关位线上。

5. 发明授权

US5428576A Semiconductor device and method of screening the same 失效
标题翻译：半导体器件及其筛选方法
公开(公告)号：US5428576A
公开(公告)日：1995-06-27
申请号：US325636
申请日：1994-10-19
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C11/408 , G11C11/409 , G11C29/00 , G11C29/06 , G11C29/46 , G11C29/50 , G11C7/00 , G11C8/00
CPC分类号： G11C11/4085 , G11C29/46 , G11C29/50 , G11C5/145 , G11C5/147 , G11C11/401
摘要： A semiconductor device comprising a plurality of circuit blocks to which various potentials, including at least one potential either raised or lowered, are assigned. The device further comprises means for selectively and reversely changing the potentials assigned to the circuit blocks.
摘要翻译：一种包括多个电路块的半导体器件，其中分配了包括至少一个升高或降低的电位的各种电位。该装置还包括用于选择性地和反向地改变分配给电路块的电位的装置。

6. 发明授权

US5343087A Semiconductor device having a substrate bias generator 失效
标题翻译：具有衬底偏置发生器的半导体器件
公开(公告)号：US5343087A
公开(公告)日：1994-08-30
申请号：US713014
申请日：1991-06-10
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： G11C11/408 , G05F3/20 , G11C11/401 , G11C11/407 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L29/78 , H03K3/01
CPC分类号： G05F3/205
摘要： A semiconductor device includes an enhancement MOS transistor formed in a semiconductor substrate and a substrate bias generator supplies a predetermined bias voltage to the substrate. The impurity concentration of the substrate is within the range in which the enhancement MOS transistor keeps the enhancement mode when the substrate potential equals to the built-in potential .PHI.B.
摘要翻译：半导体器件包括形成在半导体衬底中的增强型MOS晶体管，衬底偏置发生器向衬底提供预定的偏置电压。当衬底电位等于内置电位PHI B时，衬底的杂质浓度在增强MOS晶体管保持增强模式的范围内。

7. 发明授权

US5287312A Dynamic random access memory 失效
标题翻译：动态随机存取存储器
公开(公告)号：US5287312A
公开(公告)日：1994-02-15
申请号：US813492
申请日：1991-12-26
申请人： Junichi Okamura , Tohru Furuyama
发明人： Junichi Okamura , Tohru Furuyama
IPC分类号： G01R31/28 , G01R31/30 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/06 , G11C29/34 , G11C29/50 , H01L21/66 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4085 , G11C11/4087 , G11C29/50 , G11C8/12 , G11C11/401
摘要： A dynamic random access memory according to the present invention comprises a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.
摘要翻译：根据本发明的动态随机存取存储器包括以行和列排列的多个动态存储器单元，连接到同一行上的存储器单元的字线，连接到同一列上的存储器单元的位线，字线选择电路，具有响应于内部地址信号选择任意一行的字线选择功能，字线驱动电压源，字线驱动电路，具有连接在字线之间的至少一个驱动MOS晶体管驱动电压源和字线，用于响应于字线选择电路的输出信号驱动字线;以及控制电路，用于响应于从外部输入的电压应力测试控制信号来控制字线驱动使得字线驱动电路在接收到外部地址信号时比在正常操作模式中选择的字线更多地驱动字线。

8. 发明授权

US5276647A Static random access memory including stress test circuitry 失效
标题翻译：静态随机存取存储器包括压力测试电路
公开(公告)号：US5276647A
公开(公告)日：1994-01-04
申请号：US813438
申请日：1991-12-26
申请人： Masataka Matsui , Tohru Furuyama , Shigeyuki Hayakawa , Kiyofumi Ochii
发明人： Masataka Matsui , Tohru Furuyama , Shigeyuki Hayakawa , Kiyofumi Ochii
IPC分类号： G11C11/413 , G01R31/28 , G11C8/12 , G11C29/00 , G11C29/02 , G11C29/06 , G11C29/50 , H01L21/8244 , H01L27/11 , G11C7/00
CPC分类号： G11C29/025 , G11C29/02 , G11C29/50 , G11C8/12 , G11C11/41
摘要： SRAM comprises a word line driving circuit selecting a predetermined number of word lines in accordance with an input address at the time of a normal operation, and simultaneously selecting all word lines or word lines, which are more than the number of word lines to be selected at the time of the normal operation, at the time of a voltage stress applying test, and a bit line load circuit applying a predetermined bias voltage to said pair of bit lines at the time of the normal operation, and controlling the bias voltage not to be applied to at least one of said pair of bit lines or applying the bias voltage, which is lower than the bias voltage at the time of the normal operation, at the time of the voltage stress test.
摘要翻译： SRAM包括字线驱动电路，其根据正常操作时的输入地址选择预定数量的字线，并且同时选择大于所选择的字线数量的所有字线或字线在正常工作时，在电压应力测试时，以及在正常工作时向所述一对位线施加预定偏置电压的位线负载电路，并且将偏置电压控制为不施加到所述一对位线中的至少一个或在电压应力测试时施加低于正常操作时的偏置电压的偏置电压。

9. 发明授权

US5148393A MOS dynamic semiconductor memory cell 失效
标题翻译： MOS动态半导体存储器单元
公开(公告)号：US5148393A
公开(公告)日：1992-09-15
申请号：US375909
申请日：1989-07-06
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： H01L27/04 , G11C11/404 , G11C11/407 , G11C11/408 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C11/404 , H01L27/10805
摘要： A semiconductor memory according to the present invention comprises a MOS dynamic semiconductor memory cell in which one terminal of a current path of one MOS transistor is connected to one capacitor element, the other terminal of the current path of the MOS transistor is connected to a bit line, and a gate electrode of the transistor is connected to a word line, wherein a substrate of the MOS transistor is not connected to a fixed potential terminal, and the potential of the substrate is switched and controlled so that the MOS transistor time-selectively becomes an enhancement type or a depletion type which can prevent a threshold voltage loss over time.

10. 发明授权

US5014245A Dynamic random access memory and method for writing data thereto 失效
标题翻译：动态随机存取存储器及其数据写入方法
公开(公告)号：US5014245A
公开(公告)日：1991-05-07
申请号：US540770
申请日：1990-06-20
申请人： Kazuyoshi Muroka , Takashi Ohsawa , Tohru Furuyama
发明人： Kazuyoshi Muroka , Takashi Ohsawa , Tohru Furuyama
IPC分类号： G11C11/409 , G11C11/4076 , G11C11/4096
CPC分类号： G11C11/4096 , G11C11/4076
摘要： A dynamic random access memory includes switching transistors connected between bit lines and a sensing amplifier. The switching transistors are made non-conductive during a first period. An internal write enable signal is supplied for a predetermined period to a data input circuit to write a data into a memory cell of the dynamic random access memory. The predetermined period is controlled to terminate after the termination of the first period at an early write mode.
摘要翻译：动态随机存取存储器包括连接在位线和感测放大器之间的开关晶体管。开关晶体管在第一周期内被制成不导电的。向数据输入电路提供预定时间段的内部写使能信号，以将数据写入到动态随机存取存储器的存储单元中。控制预定周期以在早期写入模式下在第一周期结束之后终止。

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