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1. 发明授权

US08357933B2 Manufacturing method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US08357933B2
公开(公告)日：2013-01-22
申请号：US12839668
申请日：2010-07-20
申请人： Akio Hasebe , Hideyuki Matsumoto , Shingo Yorisaki , Yasuhiro Motoyama , Masayoshi Okamoto , Yasunori Narizuka , Naoki Okamoto
发明人： Akio Hasebe , Hideyuki Matsumoto , Shingo Yorisaki , Yasuhiro Motoyama , Masayoshi Okamoto , Yasunori Narizuka , Naoki Okamoto
IPC分类号： H01L21/66
CPC分类号： H01L24/10 , G01R31/2889 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05085 , H01L2224/05124 , H01L2224/05144 , H01L2224/05155 , H01L2224/05166 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01046 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/12036 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15788 , H01L2924/00 , H01L2924/00014
摘要： A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.
摘要翻译：在探针测试时，探针与测试垫接触，而不会破坏芯片中形成的电路。因此，通过用螺母和螺栓固定，将装载夹具，压制工具，弹性体，粘合环和柱塞制成一体。安装在弹簧保持夹具和负载夹具之间的弹簧的弹力用于使得用作这些弹簧的构件可以朝向垫PD压下。从弹簧传递到柱塞到薄膜片的推力仅用于薄膜片的延伸。

2. 发明授权

US07901958B2 Fabrication method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07901958B2
公开(公告)日：2011-03-08
申请号：US12853360
申请日：2010-08-10
申请人： Masayoshi Okamoto , Yoshiaki Hasegawa , Yasuhiro Motoyama , Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Ryuji Shibata , Yasunori Narizuka , Akira Yabushita , Toshiyuki Majima
发明人： Masayoshi Okamoto , Yoshiaki Hasegawa , Yasuhiro Motoyama , Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Ryuji Shibata , Yasunori Narizuka , Akira Yabushita , Toshiyuki Majima
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L22/14 , G01R1/06711 , G01R1/06744 , G01R1/07307 , G01R3/00 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/49171 , H01L2924/014 , H01L2924/3011 , H01L2924/00
摘要： To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.
摘要翻译：为了允许具有金字塔或梯形金字塔形式的窄间距探针设置的测试焊盘的半导体集成电路器件进行电气测试，是由依次层叠铑膜和镍膜而形成的金属膜形成的。在互连和金属膜之间的聚酰亚胺膜中形成通孔，并且互连电连接到金属膜。通过将配备有另一个探针和通孔的另一金属膜的平面图案转过预定角度，获得装配有一个探针和通孔的金属膜之一的平面图案。

3. 发明申请

US20100277192A1 MANUFACTORING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US20100277192A1
公开(公告)日：2010-11-04
申请号：US12839668
申请日：2010-07-20
申请人： Akio HASEBE , Hideyuki MATSUMOTO , Shingo YORISAKI , Yasuhiro MOTOYAMA , Masayoshi OKAMOTO , Yasunori NARIZUKA , Naoki OKAMOTO
发明人： Akio HASEBE , Hideyuki MATSUMOTO , Shingo YORISAKI , Yasuhiro MOTOYAMA , Masayoshi OKAMOTO , Yasunori NARIZUKA , Naoki OKAMOTO
IPC分类号： G01R1/06
CPC分类号： H01L24/10 , G01R31/2889 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05085 , H01L2224/05124 , H01L2224/05144 , H01L2224/05155 , H01L2224/05166 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01046 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/12036 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15788 , H01L2924/00 , H01L2924/00014
摘要： A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.
摘要翻译：在探针测试时，探针与测试垫接触，而不会破坏芯片中形成的电路。因此，通过用螺母和螺栓固定，将装载夹具，压制工具，弹性体，粘合环和柱塞制成一体。安装在弹簧保持夹具和负载夹具之间的弹簧的弹力用于使得用作这些弹簧的构件可以朝向垫PD压下。从弹簧传递到柱塞到薄膜片的推力仅用于薄膜片的延伸。

4. 发明授权

US07407823B2 Manufacturing method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07407823B2
公开(公告)日：2008-08-05
申请号：US11471712
申请日：2006-06-21
申请人： Akio Hasebe , Masayoshi Okamoto , Yasunori Narizuka , Shingo Yorisaki , Yasuhiro Motoyama
发明人： Akio Hasebe , Masayoshi Okamoto , Yasunori Narizuka , Shingo Yorisaki , Yasuhiro Motoyama
IPC分类号： H01L21/66
CPC分类号： G01R3/00 , G01R1/07378 , G01R31/2889
摘要： During probe testing using a prober having probe needles formed by using a manufacturing technology for a semiconductor integrated circuit device, reliable contact is ensured between the probe needles and test pads. A pressing tool having at least one hole portion formed therein and extending therethrough between the main and back surface thereof is prepared. An elastomer in the form of a sheet and a polyimide sheet are successively disposed on the main surface of the pressing tool. With th elastomer and the polyimide sheet being electrostatically attracted to the pressing tool, the pressing tool is disposed on a thin-film sheet such that the main surface thereof faces the back surface (the surface opposite to the main surface thereof formed with the probe) of the thin-film sheet. Then, the thin-film sheet with the pressing tool bonded thereto is attached to a probe card.
摘要翻译：在使用具有通过使用用于半导体集成电路器件的制造技术形成的探针的探针的探针测试期间，确保探针和测试垫之间的可靠接触。制备具有形成在其中并在其主表面和后表面之间延伸穿过其中的至少一个孔部分的按压工具。在压制工具的主表面上依次设置片状和聚酰亚胺片形式的弹性体。利用弹性体，将聚酰亚胺片静电吸引到按压工具上，将压制工具设置在薄膜片上，使其主表面面向背面（与形成有探针的主表面相反的表面）的薄膜片。然后，将与其接合的按压工具的薄膜片安装在探针卡上。

5. 发明授权

US07219422B2 Fabrication method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07219422B2
公开(公告)日：2007-05-22
申请号：US10765917
申请日：2004-01-29
申请人： Yuji Wada , Susumu Kasukabe , Takehiko Hasebe , Yasunori Narizuka , Akira Yabushita , Terutaka Mori , Akio Hasebe , Yasuhiro Motoyama , Teruo Shoji , Masakazu Sueyoshi
发明人： Yuji Wada , Susumu Kasukabe , Takehiko Hasebe , Yasunori Narizuka , Akira Yabushita , Terutaka Mori , Akio Hasebe , Yasuhiro Motoyama , Teruo Shoji , Masakazu Sueyoshi
IPC分类号： H05K3/00 , H01R9/00
CPC分类号： G01R1/07314 , G01R31/2872 , Y10T29/41 , Y10T29/49128 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49798
摘要： The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.
摘要翻译：半导体集成电路器件的制造包括使用推压机构进行测试，所述推压机构通过在薄膜探针的上表面上形成具有几乎等于晶片的线性膨胀系数（热膨胀系数）的增强材料而构成待测在接触端子上方的增强材料中形成凹槽; 将弹性体放置在所述槽中，使得预定量突出到所述凹槽中; 并且设置推进器和另一种弹性体以将推进器夹在弹性体之间。通过使用这样的探针，可以提高半导体集成电路的晶片级电气测试的吞吐量。

6. 发明申请

US20070108997A1 FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROBE CARD 失效
标题翻译：半导体集成电路器件和探针卡的制造方法
公开(公告)号：US20070108997A1
公开(公告)日：2007-05-17
申请号：US11555993
申请日：2006-11-02
申请人： Yasuhiro Motoyama , Yoshimi Horigome , Seigo Nakamura , Iwao Natori
发明人： Yasuhiro Motoyama , Yoshimi Horigome , Seigo Nakamura , Iwao Natori
IPC分类号： G01R31/02
CPC分类号： G01R1/07314
摘要： To provide a technique of firmly bringing a stylus and a test pad into contact with each other in carrying out a probe testing summarizingly for plural chips by using a prober having the stylus formed by a technique of manufacturing a semiconductor integrated circuit device, plane patterns of respective wirings are formed such that a wiring and a wiring electrically connected to the wiring or a wiring which is not electrically connected to the wiring overlap each other, and a plane pattern arranged with both of the wiring and the wiring is constituted at upper portions of probes. Further, patterns of the wirings are formed such that an interval of arranging the wirings and a density of arranging the wirings become uniform at respective wiring layers in a thin film sheet.
摘要翻译：为了提供一种牢固地使触针和测试垫彼此接触的技术，通过使用具有通过制造半导体集成电路器件的技术形成的触针的探针来对多个芯片进行总体测试测试，其平面图案各布线形成为使布线和与布线电连接的布线或与布线不电连接的布线重叠，并且布置在布线和布线两者中的平面图形被构成在探针。此外，布线的图案形成为使得布线布置的间隔和布线的密度在薄膜片的各个布线层处变得均匀。

7. 发明授权

US06696849B2 Fabrication method of semiconductor integrated circuit device and its testing apparatus 有权
标题翻译：半导体集成电路器件及其测试装置的制造方法
公开(公告)号：US06696849B2
公开(公告)日：2004-02-24
申请号：US09964708
申请日：2001-09-28
申请人： Naoto Ban , Masaaki Namba , Akio Hasebe , Yuji Wada , Ryuji Kohno , Akira Seito , Yasuhiro Motoyama
发明人： Naoto Ban , Masaaki Namba , Akio Hasebe , Yuji Wada , Ryuji Kohno , Akira Seito , Yasuhiro Motoyama
IPC分类号： G01R3102
CPC分类号： G01R31/2831
摘要： A testing apparatus and a fabricating method of a semiconductor integrated circuit device for reducing the fabrication cost by placing, in the wafer level burn-in, divided contactors in equally contact with the full surface of wafer, enabling repair of each contactor and improving the yield of contactors. The cassette structure of the mechanical pressurizing system in the testing apparatus is structured with a plurality of divided silicon contactor blocks and a guide frame for integrating these blocks and employs the wafer full surface simultaneous contact system of the divided contactor integration type. Each probe of the silicon contactor is equally placed in contact in the predetermined pressure with each test pad of each chip of the test wafer by mechanically pressuring each silicon contactor block which moves individually, the test control signal is supplied to each chip and this test result signal is obtained for the wafer level burn-in test.
摘要翻译：一种半导体集成电路器件的测试装置和制造方法，用于通过在晶片级老化中放置与晶片的整个表面均匀接触的分割的接触器来降低制造成本，从而能够修复每个接触器并提高产量的接触器。测试装置中的机械加压系统的盒式结构由多个分开的硅接触器块和用于集成这些块的引导框架构成，并且采用分开的接触器一体化型的晶片全表面同时接触系统。硅接触器的每个探针通过机械加压每个单独移动的硅接触器块，将测试控制信号提供给每个芯片，并且测试结果与测试晶片的每个芯片的每个测试焊盘等同地以预定压力接触获得晶片级老化测试信号。

8. 发明授权

US06197603B1 Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step 失效
标题翻译：半导体器件及其制造方法，包括探针测试步骤和老化测试步骤
公开(公告)号：US06197603B1
公开(公告)日：2001-03-06
申请号：US09157153
申请日：1998-09-18
申请人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
发明人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
IPC分类号： G01R3126
CPC分类号： G01R3/00 , G01R1/0735
摘要： Dispersion of a load may be kept within a predetermined allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane against a wafer by applying a pressure load to a plurality of places on a plane of the pressure members on the side opposite the wafer in a probe test step, burn-in test step which represent typical semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit at the same time.
摘要翻译：即使当大量区域中的多个探针通过将设置在膜中的探针压在晶片上时，通过将压力负载施加到多个位置的平面上的多个位置，负载的分散也可以保持在预定容限内在探针测试步骤中与晶片相对的一侧的压力构件，代表典型的半导体器件制造步骤的老化测试步骤。因此，可以提供通过同时探测大量集成电路或大尺寸集成电路来提高半导体器件的可靠性和生产率的半导体器件及其制造方法。

9. 发明授权

US08323992B2 Method of manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US08323992B2
公开(公告)日：2012-12-04
申请号：US13228334
申请日：2011-09-08
申请人： Seigo Nakamura , Iwao Natori , Yasuhiro Motoyama
发明人： Seigo Nakamura , Iwao Natori , Yasuhiro Motoyama
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： G01R31/2889 , G01R1/07314 , G01R1/0735
摘要： The variation in the contact pressures of the plurality of contact terminals to the plurality of chip electrodes is decreased. A thin-film sheet (first sheet) includes: a principal surface (contact-terminal formation surface) on which a plurality of contactors (contact terminals) are formed; and a rear surface positioned on an opposite side to the principal surface. Also, in the thin film sheet, a plurality of wirings and dummy wiring are arranged between the principal surface and the rear surface. A slit formed of an opening portion penetrating from the principal surface of the thin-film sheet to the rear surface thereof is formed along the wiring between the dummy wiring and the contactor arranged at an end of a contactor group (first contact terminal group) in which the plurality of contactors are aligned.
摘要翻译：多个接触端子对多个芯片电极的接触压力的变化减小。薄膜片（第一片）包括：形成有多个接触器（接触端子）的主表面（接触端子形成表面）; 以及位于与主表面相对的一侧的后表面。此外，在薄膜片中，在主面和背面之间配置有多根配线和虚设布线。沿着布置在接触器组（第一接触端子组）的端部处的虚设布线和接触器之间的布线，形成有从薄膜片的主表面贯穿其后表面的开口部分形成的狭缝，多个接触器对齐。

10. 发明授权

US08062911B2 Method of manufacturing a semiconductor integrated circuit device and a method of manufacturing a thin film probe sheet for using the same 有权
标题翻译：半导体集成电路器件的制造方法以及使用该半导体集成电路器件的薄膜探针片的制造方法
公开(公告)号：US08062911B2
公开(公告)日：2011-11-22
申请号：US11958369
申请日：2007-12-17
申请人： Akio Hasebe , Yasuhiro Motoyama , Yasunori Narizuka , Seigo Nakamura , Kenji Kawakami
发明人： Akio Hasebe , Yasuhiro Motoyama , Yasunori Narizuka , Seigo Nakamura , Kenji Kawakami
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： G01R3/00 , G01R1/07342
摘要： A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.
摘要翻译：通过选择性地在晶片的主表面上沉积在要形成金属膜的区域中的铜膜和当探针卡是在粘合环外部时将在粘合环外部的区域，制造具有足够高度的探针制造的形成金属膜，聚酰亚胺膜，互连，另一聚酰亚胺膜，另一互连和另外的聚酰亚胺膜; 然后取出晶片和铜膜。根据本发明，在利用半导体集成电路器件的制造技术的情况下，使用具有以上述方式形成的探针的探测器（薄膜探针）进行探针测试时，可以防止探测器的破损，待测试的晶圆。

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