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1. 发明授权

US07981735B2 Method of manufacturing a Schottky barrier tunnel transistor 失效
标题翻译：制造肖特基势垒隧道晶体管的方法
公开(公告)号：US07981735B2
公开(公告)日：2011-07-19
申请号：US12434779
申请日：2009-05-04
申请人： Yark Yeon Kim , Seong Jae Lee , Moon Gyu Jang , Chel Jong Choi , Myung Sim Jun , Byoung Chul Park
发明人： Yark Yeon Kim , Seong Jae Lee , Moon Gyu Jang , Chel Jong Choi , Myung Sim Jun , Byoung Chul Park
IPC分类号： H01L21/336
CPC分类号： H01L29/47 , H01L29/458 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/7839
摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.
摘要翻译：提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道来最小化对肖特基势垒隧道晶体管的栅极侧壁的损坏所造成的漏电流屏障。该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

2. 发明申请

US20110068326A1 SCHOTTKY BARRIER TUNNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：肖特基BARRIER隧道晶体管及其制造方法
公开(公告)号：US20110068326A1
公开(公告)日：2011-03-24
申请号：US12957146
申请日：2010-11-30
申请人： Moon-Gyu Jang , Yark-Yeon Kim , Chel-Jong Choi , Myung-Sim Jun , Tae-Youb Kim , Seong-Jae Lee
发明人： Moon-Gyu Jang , Yark-Yeon Kim , Chel-Jong Choi , Myung-Sim Jun , Tae-Youb Kim , Seong-Jae Lee
IPC分类号： H01L29/78
CPC分类号： H01L29/8126 , H01L29/66409
摘要： A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.
摘要翻译：肖特基势垒隧道晶体管包括栅极电极和源极和漏极区域。栅电极形成在衬底的沟道区上，以与衬底形成肖特基结。源极和漏极区域形成在暴露于栅电极两侧的衬底中。

3. 发明授权

US07745316B2 Method for fabricating Schottky barrier tunnel transistor 失效
标题翻译：制造肖特基势垒隧道晶体管的方法
公开(公告)号：US07745316B2
公开(公告)日：2010-06-29
申请号：US11930902
申请日：2007-10-31
申请人： Yark-Yeon Kim , Seong-Jae Lee , Moon-Gyu Jang , Tae-Youb Kim , Chel-Jong Choi , Myung-Sim Jun , Byoung-Chul Park
发明人： Yark-Yeon Kim , Seong-Jae Lee , Moon-Gyu Jang , Tae-Youb Kim , Chel-Jong Choi , Myung-Sim Jun , Byoung-Chul Park
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L29/78618 , H01L29/7839
摘要： Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.
摘要翻译：提供一种用于制造肖特基势垒隧道晶体管（SBTT）的方法，其可以从根本上防止由栅极电极的两个侧壁上形成的间隔物的损坏引起的栅极漏电流的产生。一种制造肖特基势垒隧道晶体管的方法，包括：a）在由支撑衬底支撑的掩埋氧化物层上形成硅图案和牺牲图案; b）在暴露于硅图案的两侧的掩埋氧化物层上形成源极/漏极区域，源极/漏极区域由金属层形成并与硅图案的两个侧壁接触; c）去除牺牲图案以暴露硅图案的顶表面; 以及d）在暴露的硅图案上形成栅极绝缘层和栅电极。

4. 发明授权

US07605065B2 Schottky barrier tunnel single electron transistor and method of manufacturing the same 有权
标题翻译：肖特基势垒隧道单电子晶体管及其制造方法
公开(公告)号：US07605065B2
公开(公告)日：2009-10-20
申请号：US11839704
申请日：2007-08-16
申请人： Moon Gyu Jang , Yark Yeon Kim , Jae Heon Shin , Seong Jae Lee
发明人： Moon Gyu Jang , Yark Yeon Kim , Jae Heon Shin , Seong Jae Lee
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/872
摘要： Provided are a Schottky barrier tunnel single electron transistor and a method of manufacturing the same that use a Schottky barrier formed between metal and semiconductor by replacing a source and a drain with silicide as a reactant of silicon and metal, instead of a conventional method of manufacturing a single electron transistor (SET) that includes source and drain regions by implanting dopants such that an artificial quantum dot is formed in a channel region. As a result, it does not require a conventional PADOX process to form a quantum dot for a single electron transistor (SET), height and width of a tunneling barrier can be artificially adjusted by using silicide materials that have various Schottky junction barriers, and it is possible to improve current driving capability of the single electron transistor (SET).
摘要翻译：提供了一种肖特基势垒隧道单电子晶体管及其制造方法，其替代传统的制造方法，而是用硅化物替代源极和漏极作为硅和金属的反应物，从而形成金属和半导体之间形成的肖特基势垒单电子晶体管（SET），其通过注入掺杂剂而包括源极和漏极区域，使得在沟道区域中形成人造量子点。结果，不需要传统的PADOX工艺来形成单电子晶体管（SET）的量子点，隧道势垒的高度和宽度可以通过使用具有各种肖特基结屏障的硅化物材料进行人工调整，而且可以提高单电子晶体管（SET）的电流驱动能力。

5. 发明授权

US07566642B2 Process of manufacturing an N-type Schottky barrier tunnel transistor 有权
标题翻译：制造N型肖特基势垒隧道晶体管的工艺
公开(公告)号：US07566642B2
公开(公告)日：2009-07-28
申请号：US11188076
申请日：2005-07-22
申请人： Yark Yeon Kim , Moon Gyu Jang , Jae Heon Shin , Seong Jae Lee
发明人： Yark Yeon Kim , Moon Gyu Jang , Jae Heon Shin , Seong Jae Lee
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/2252 , H01L21/2254 , H01L21/28518 , H01L21/28537 , H01L29/458 , H01L29/4908 , H01L29/66636 , H01L29/7834 , H01L29/7839
摘要： An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.
摘要翻译：提供了n型SBTT及其制造方法。 SBTT包括硅层，栅极，具有稀土金属硅化物层和过渡金属硅化物层的双层。硅层具有沟道区。栅极以重叠的方式形成在沟道区上，并且在其相对于硅层的界面上具有栅极介电层。双层形成为具有介于硅层之间的沟道区的源极/漏极。

6. 发明申请

US20130149532A1 FIBER FABRICATION METHOD AND THE FIBER FABRICATED THEREBY 有权
标题翻译：纤维制造方法和纤维制造方法
公开(公告)号：US20130149532A1
公开(公告)日：2013-06-13
申请号：US13592270
申请日：2012-08-22
申请人： Yong Ju Yun , Zin Sig Kim , Han Young Yu , Yark Yeon Kim , Won Ick Jang
发明人： Yong Ju Yun , Zin Sig Kim , Han Young Yu , Yark Yeon Kim , Won Ick Jang
IPC分类号： B29C47/12 , D01F9/12 , D01F9/00 , D02G3/04 , B82Y30/00
CPC分类号： B29C47/0014 , B29C47/04 , B29C47/12 , B82Y30/00 , D01D5/0038 , D01D5/0069 , D01D5/38 , D01F6/60 , Y10T428/2931
摘要： Provided are fiber fabrication method and the fiber fabricated thereby. In this method, different monomer solutions are electrospun through nozzles whose outlets are stuck to each other and simultaneously interfacially polymerized to form a polymer fiber without a complicated process of preparing a polymer solution. Therefore, a polymer fiber can be simply prepared.
摘要翻译：提供了纤维制造方法和由此制造的纤维。在这种方法中，不同的单体溶液通过喷嘴进行静电纺丝，其出口彼此粘合并同时进行界面聚合以形成聚合物纤维，而不需要制备聚合物溶液的复杂工艺。因此，可以简单地制备聚合物纤维。

7. 发明授权

US08283654B2 Nanowire memory 有权
标题翻译：纳米线记忆
公开(公告)号：US08283654B2
公开(公告)日：2012-10-09
申请号：US12621809
申请日：2009-11-19
申请人： Han Young Yu , Byung Hoon Kim , Soon Young Oh , Yong Ju Yun , Yark Yeon Kim , Won Gi Hong
发明人： Han Young Yu , Byung Hoon Kim , Soon Young Oh , Yong Ju Yun , Yark Yeon Kim , Won Gi Hong
IPC分类号： H01L29/06 , H01L35/24 , H01L31/0312 , H01L29/792 , H01L31/0328
CPC分类号： H01L29/775 , B82Y10/00 , H01L27/10873 , H01L29/0665 , H01L29/0673 , H01L29/685
摘要： Provided is a nanowire memory including a source and a drain corresponding to the source, and a nano channel formed to connect the source to the drain. Here, the nano channel includes a nanowire electrically connecting the source to the drain according to voltages of the source and drain, and a nanodot formed on the nanowire and having a plurality of potentials capturing charges. Thus, the nanowire memory has a simple structure, thereby simplifying a process. It can generate multi current levels by adjusting several energy states using gates, operate as a volatile or non-volatile memory by adjusting the gates and the energy level, and include another gate configured to adjust the energy level, resulting in formation of a hybrid structure of volatile and non-volatile memories.
摘要翻译：提供了纳米线存储器，其包括对应于源极的源极和漏极，以及形成为将源极连接到漏极的纳米通道。这里，纳米通道包括根据源极和漏极的电压将源极与漏极电连接的纳米线，以及形成在纳米线上并具有捕获电荷的多个电位的纳米点。因此，纳米线存储器具有简单的结构，从而简化了工艺。它可以通过使用门调节几个能量状态来产生多个电流电平，通过调整栅极和能量水平来操作为易失性或非易失性存储器，并且包括配置成调整能级的另一个门，从而形成混合结构的易失性和非易失性存储器。

8. 发明申请

US20100314609A1 NANOWIRE MEMORY 有权
标题翻译： NANOWIRE记忆
公开(公告)号：US20100314609A1
公开(公告)日：2010-12-16
申请号：US12621809
申请日：2009-11-19
申请人： Han Young YU , Byung Hoon Kim , Soon Young Oh , Yong Ju Yun , Yark Yeon Kim , Won Gi Hong
发明人： Han Young YU , Byung Hoon Kim , Soon Young Oh , Yong Ju Yun , Yark Yeon Kim , Won Gi Hong
IPC分类号： H01L29/775
CPC分类号： H01L29/775 , B82Y10/00 , H01L27/10873 , H01L29/0665 , H01L29/0673 , H01L29/685
摘要： Provided is a nanowire memory including a source and a drain corresponding to the source, and a nano channel formed to connect the source to the drain. Here, the nano channel includes a nanowire electrically connecting the source to the drain according to voltages of the source and drain, and a nanodot formed on the nanowire and having a plurality of potentials capturing charges. Thus, the nanowire memory has a simple structure, thereby simplifying a process. It can generate multi current levels by adjusting several energy states using gates, operate as a volatile or non-volatile memory by adjusting the gates and the energy level, and include another gate configured to adjust the energy level, resulting in formation of a hybrid structure of volatile and non-volatile memories.
摘要翻译：提供了纳米线存储器，其包括对应于源极的源极和漏极，以及形成为将源极连接到漏极的纳米通道。这里，纳米通道包括根据源极和漏极的电压将源极与漏极电连接的纳米线，以及形成在纳米线上并具有捕获电荷的多个电位的纳米点。因此，纳米线存储器具有简单的结构，从而简化了工艺。它可以通过使用门调节几个能量状态来产生多个电流电平，通过调整栅极和能量水平来操作为易失性或非易失性存储器，并且包括被配置为调整能量水平的另一个栅极，从而形成混合结构的易失性和非易失性存储器。

9. 发明申请

US20090250756A1 N-TYPE SCHOTTKY BARRIER TUNNEL TRANSISTOR AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译： N型肖特基隧道式隧道式晶体管及其制造方法
公开(公告)号：US20090250756A1
公开(公告)日：2009-10-08
申请号：US12485777
申请日：2009-06-16
申请人： Yark Yeon Kim , Moon Gyu Jang , Jae Heon Shin , Seong Jae Lee
发明人： Yark Yeon Kim , Moon Gyu Jang , Jae Heon Shin , Seong Jae Lee
IPC分类号： H01L27/12
CPC分类号： H01L29/665 , H01L21/2252 , H01L21/2254 , H01L21/28518 , H01L21/28537 , H01L29/458 , H01L29/4908 , H01L29/66636 , H01L29/7834 , H01L29/7839
摘要： An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.
摘要翻译：提供了n型SBTT及其制造方法。 SBTT包括硅层，栅极，具有稀土金属硅化物层和过渡金属硅化物层的双层。硅层具有沟道区。栅极以重叠的方式形成在沟道区上，并且在其相对于硅层的界面上具有栅极介电层。双层形成为具有介于硅层之间的沟道区的源极/漏极。

10. 发明申请

US20080128786A1 HIGH DENSITY SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：高密度半导体存储器件及其制造方法
公开(公告)号：US20080128786A1
公开(公告)日：2008-06-05
申请号：US11950291
申请日：2007-12-04
申请人： Taeyoub KIM , Myungsim JUN , Yark-Yeon KIM , Moon-Gyu JANG , Chel-Jong CHOI , Seong-Jae LEE , Byoungchul PARK
发明人： Taeyoub KIM , Myungsim JUN , Yark-Yeon KIM , Moon-Gyu JANG , Chel-Jong CHOI , Seong-Jae LEE , Byoungchul PARK
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/788 , B82Y10/00 , H01L29/40114 , H01L29/41725 , H01L29/42324 , H01L29/47 , H01L29/66825 , H01L29/7839 , H01L29/78654 , H01L29/7881
摘要： Provided are a high density semiconductor memory device capable of precisely reading data by suppressing the occurrence of a leakage current due to the high-integration of the semiconductor memory device, and a method for manufacturing the semiconductor memory device. The high density semiconductor memory device includes: source and drain electrodes disposed over a substrate, and forming a Schottky junction with a channel region; and a floating gate disposed over the substrate of the channel region, and configured with a plurality of nanodots. The nanodots may be formed of a silicon compound or any material that can be charged.
摘要翻译：提供一种能够通过抑制由于半导体存储器件的高集成度而导致的漏电流的发生而精确读取数据的高密度半导体存储器件以及半导体存储器件的制造方法。高密度半导体存储器件包括：源极和漏极，设置在衬底上，并与沟道区形成肖特基结; 以及浮置栅极，设置在沟道区域的衬底上，并且配置有多个纳米点。纳米点可以由硅化合物或可以被充电的任何材料形成。

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