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1. 发明授权

US07605065B2 Schottky barrier tunnel single electron transistor and method of manufacturing the same 有权
标题翻译：肖特基势垒隧道单电子晶体管及其制造方法
公开(公告)号：US07605065B2
公开(公告)日：2009-10-20
申请号：US11839704
申请日：2007-08-16
申请人： Moon Gyu Jang , Yark Yeon Kim , Jae Heon Shin , Seong Jae Lee
发明人： Moon Gyu Jang , Yark Yeon Kim , Jae Heon Shin , Seong Jae Lee
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/872
摘要： Provided are a Schottky barrier tunnel single electron transistor and a method of manufacturing the same that use a Schottky barrier formed between metal and semiconductor by replacing a source and a drain with silicide as a reactant of silicon and metal, instead of a conventional method of manufacturing a single electron transistor (SET) that includes source and drain regions by implanting dopants such that an artificial quantum dot is formed in a channel region. As a result, it does not require a conventional PADOX process to form a quantum dot for a single electron transistor (SET), height and width of a tunneling barrier can be artificially adjusted by using silicide materials that have various Schottky junction barriers, and it is possible to improve current driving capability of the single electron transistor (SET).
摘要翻译：提供了一种肖特基势垒隧道单电子晶体管及其制造方法，其替代传统的制造方法，而是用硅化物替代源极和漏极作为硅和金属的反应物，从而形成金属和半导体之间形成的肖特基势垒单电子晶体管（SET），其通过注入掺杂剂而包括源极和漏极区域，使得在沟道区域中形成人造量子点。结果，不需要传统的PADOX工艺来形成单电子晶体管（SET）的量子点，隧道势垒的高度和宽度可以通过使用具有各种肖特基结屏障的硅化物材料进行人工调整，而且可以提高单电子晶体管（SET）的电流驱动能力。

2. 发明授权

US07566642B2 Process of manufacturing an N-type Schottky barrier tunnel transistor 有权
标题翻译：制造N型肖特基势垒隧道晶体管的工艺
公开(公告)号：US07566642B2
公开(公告)日：2009-07-28
申请号：US11188076
申请日：2005-07-22
申请人： Yark Yeon Kim , Moon Gyu Jang , Jae Heon Shin , Seong Jae Lee
发明人： Yark Yeon Kim , Moon Gyu Jang , Jae Heon Shin , Seong Jae Lee
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/2252 , H01L21/2254 , H01L21/28518 , H01L21/28537 , H01L29/458 , H01L29/4908 , H01L29/66636 , H01L29/7834 , H01L29/7839
摘要： An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.
摘要翻译：提供了n型SBTT及其制造方法。 SBTT包括硅层，栅极，具有稀土金属硅化物层和过渡金属硅化物层的双层。硅层具有沟道区。栅极以重叠的方式形成在沟道区上，并且在其相对于硅层的界面上具有栅极介电层。双层形成为具有介于硅层之间的沟道区的源极/漏极。

3. 发明申请

US20090250756A1 N-TYPE SCHOTTKY BARRIER TUNNEL TRANSISTOR AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译： N型肖特基隧道式隧道式晶体管及其制造方法
公开(公告)号：US20090250756A1
公开(公告)日：2009-10-08
申请号：US12485777
申请日：2009-06-16
申请人： Yark Yeon Kim , Moon Gyu Jang , Jae Heon Shin , Seong Jae Lee
发明人： Yark Yeon Kim , Moon Gyu Jang , Jae Heon Shin , Seong Jae Lee
IPC分类号： H01L27/12
CPC分类号： H01L29/665 , H01L21/2252 , H01L21/2254 , H01L21/28518 , H01L21/28537 , H01L29/458 , H01L29/4908 , H01L29/66636 , H01L29/7834 , H01L29/7839
摘要： An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.
摘要翻译：提供了n型SBTT及其制造方法。 SBTT包括硅层，栅极，具有稀土金属硅化物层和过渡金属硅化物层的双层。硅层具有沟道区。栅极以重叠的方式形成在沟道区上，并且在其相对于硅层的界面上具有栅极介电层。双层形成为具有介于硅层之间的沟道区的源极/漏极。

4. 发明授权

US07312510B2 Device using ambipolar transport in SB-MOSFET and method for operating the same 失效
标题翻译：在SB-MOSFET中使用双极传输的器件及其操作方法
公开(公告)号：US07312510B2
公开(公告)日：2007-12-25
申请号：US11187654
申请日：2005-07-22
申请人： Jae Heon Shin , Moon Gyu Jang , Yark Yeon Kim , Seong Jae Lee
发明人： Jae Heon Shin , Moon Gyu Jang , Yark Yeon Kim , Seong Jae Lee
IPC分类号： H01L29/47
CPC分类号： H01L29/7839 , G11C11/56
摘要： A device using an ambipolar transport of an SB-MOSFET and a method for operating the same are provided. The SB-MOSFET includes: a silicon channel region; a source and a drain contacted on both sides of the channel region and formed of material including metal layer; and a gate formed on the channel region, with a gate dielectric layer interposed therebetween. Positive (+), 0 or negative (−) gate voltage is selectively applied to the gate, the channel becomes off-state when the gate voltage between a negative threshold voltage and a positive threshold voltage is applied, and the channel becomes a first on-state and a second on-state when the gate voltage is lower than the negative threshold voltage or higher than the positive threshold voltage. Accordingly, it is possible to implement three current states, that is, hole current, electron current, and no current. The SB-MOSFET can be applied to a multi-bit memory and/or multi-bit logic device.
摘要翻译：提供了使用SB-MOSFET的双极运输的装置及其操作方法。 SB-MOSFET包括：硅沟道区; 源极和漏极在沟道区域的两侧接触并由包括金属层的材料形成; 以及形成在沟道区上的栅极，介于其间的栅介质层。正极（+），0或负（ - ）栅极电压选择性地施加到栅极，当施加负阈值电压和正阈值电压之间的栅极电压时，通道变为截止状态，并且通道变为第一个当门电压低于负阈值电压或高于正阈值电压时，状态和第二导通状态。因此，可以实现三种电流状态，即空穴电流，电子电流，无电流。 SB-MOSFET可以应用于多位存储器和/或多位逻辑器件。

5. 发明授权

US07268407B2 Schottky barrier tunnel single electron transistor and method of manufacturing the same 失效
标题翻译：肖特基势垒隧道单电子晶体管及其制造方法
公开(公告)号：US07268407B2
公开(公告)日：2007-09-11
申请号：US11196180
申请日：2005-08-03
申请人： Moon Gyu Jang , Yark Yeon Kim , Jae Heon Shin , Seong Jae Lee
发明人： Moon Gyu Jang , Yark Yeon Kim , Jae Heon Shin , Seong Jae Lee
IPC分类号： H01L31/07
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/872
摘要： Provided are a Schottky barrier tunnel single electron transistor and a method of manufacturing the same that use a Schottky barrier formed between metal and semiconductor by replacing a source and a drain with silicide as a reactant of silicon and metal, instead of a conventional method of manufacturing a single electron transistor (SET) that includes source and drain regions by implanting dopants such that an artificial quantum dot is formed in a channel region. As a result, it does not require a conventional PADOX process to form a quantum dot for a single electron transistor (SET), height and width of a tunneling barrier can be artificially adjusted by using silicide materials that have various Schottky junction barriers, and it is possible to improve current driving capability of the single electron transistor (SET).
摘要翻译：提供了一种肖特基势垒隧道单电子晶体管及其制造方法，其替代传统的制造方法，而是用硅化物替代源极和漏极作为硅和金属的反应物，从而形成金属和半导体之间形成的肖特基势垒单电子晶体管（SET），其通过注入掺杂剂而包括源极和漏极区域，使得在沟道区域中形成人造量子点。结果，不需要传统的PADOX工艺来形成单电子晶体管（SET）的量子点，隧道势垒的高度和宽度可以通过使用具有各种肖特基结屏障的硅化物材料进行人工调整，而且可以提高单电子晶体管（SET）的电流驱动能力。

6. 发明授权

US08095343B2 Method and apparatus for modeling source-drain current of thin film transistor 有权
标题翻译：薄膜晶体管源漏电流建模方法及设备
公开(公告)号：US08095343B2
公开(公告)日：2012-01-10
申请号：US12201457
申请日：2008-08-29
申请人： Jae Heon Shin , Chi Sun Hwang , Min Ki Ryu , Woo Seok Cheong , Hye Yong Chu
发明人： Jae Heon Shin , Chi Sun Hwang , Min Ki Ryu , Woo Seok Cheong , Hye Yong Chu
IPC分类号： G06F17/11
CPC分类号： G06F17/5036
摘要： Provided are a method and apparatus for modeling source-drain current of a TFT. The method includes receiving sample data, the sample data including a sample input value and a sample output value; adjusting modeling variables according to the sample data; calculating a current model value according to the adjusted modeling variables; when a difference between the calculated current model value and the sample output value is smaller than a predetermined threshold value, fitting a current model by applying the adjusted modeling variables to the current model; applying actual input data to the fitted current model; and outputting a result value corresponding to the actual input data, wherein the current model is a model for predicting the source-drain current of the TFT.
摘要翻译：提供了一种用于建模TFT的源极 - 漏极电流的方法和装置。该方法包括接收样本数据，样本数据包括样本输入值和样本输出值; 根据样本数据调整建模变量; 根据调整后的建模变量计算当前模型值; 当所计算的当前模型值与样本输出值之间的差小于预定阈值时，通过将调整的建模变量应用于当前模型来拟合当前模型; 将实际输入数据应用于拟合的当前模型; 并输出与实际输入数据对应的结果值，其中当前模型是用于预测TFT的源极 - 漏极电流的模型。

7. 发明授权

US07772587B2 Silicon-based light emitting diode for enhancing light extraction efficiency and method of fabricating the same 有权
标题翻译：用于提高光提取效率的硅基发光二极管及其制造方法
公开(公告)号：US07772587B2
公开(公告)日：2010-08-10
申请号：US12096764
申请日：2006-03-14
申请人： Kyung Hyun Kim , Nae Man Park , Chul Huh , Tae Youb Kim , Jae Heon Shin , Kwan Sik Cho , Gun Yong Sung
发明人： Kyung Hyun Kim , Nae Man Park , Chul Huh , Tae Youb Kim , Jae Heon Shin , Kwan Sik Cho , Gun Yong Sung
IPC分类号： H01L29/06 , H01L21/00
CPC分类号： H01L33/44 , H01L33/10 , H01L33/20 , H01L33/22 , H01L33/34 , H01L33/38 , H01L2933/0091
摘要： Due to the indirect transition characteristic of silicon semiconductors, the light extraction efficiency of a silicon-based light emitting diode is lower than that of a compound semiconductor-based light emitting diode. For this reason, there are difficulties in practically using and commercializing silicon-based light emitting diodes developed so far. Provided is a silicon-based light emitting including: a substrate with a lower electrode layer on a lower surface thereof; a lower doped layer that is formed on an upper surface of the substrate and supplies carriers to an emitting layer; the emitting layer that is a silicon semiconductor layer including silicon quantum dots or nanodots formed on the lower doped layer and has a light-emitting characteristic; an upper doped layer that is formed on the emitting layer and supplies carriers to the emitting layer; an upper electrode layer formed on the upper doped layer; and a surface structure including a surface pattern formed on the upper electrode layer, a surface structure including an upper electrode pattern and an upper doped pattern formed by patterning the upper electrode layer and the upper doped layer, or a surface structure including the surface pattern, the upper electrode pattern, and upper doped pattern, wherein the surface structure enhances the light extraction efficiency of light emitted from the emitting layer according to geometric optics.
摘要翻译：由于硅半导体的间接跃迁特性，硅基发光二极管的光提取效率低于基于化合物半导体的发光二极管的光提取效率。因此，实际上使用和商业化目前为止开发的硅基发光二极管存在困难。本发明提供一种硅基发光体，具有：下表面具有下电极层的基板; 下部掺杂层，其形成在所述衬底的上表面上并将载体提供给发光层; 所述发光层是包含形成在所述下掺杂层上的硅量子点或纳米点的具有发光特性的硅半导体层; 上部掺杂层，其形成在所述发光层上并将载流子提供给所述发光层; 形成在上掺杂层上的上电极层; 以及包括形成在上电极层上的表面图案的表面结构，包括通过图案化上电极层和上掺杂层形成的上电极图案和上掺杂图案的表面结构，或包括表面图案的表面结构，上电极图案和上掺杂图案，其中表面结构根据几何光学增强了从发光层发射的光的光提取效率。

8. 发明授权

US06727109B2 Method of fabricating long wavelength vertical-cavity surface-emitting lasers 失效
标题翻译：制造长波长垂直腔表面发射激光器的方法
公开(公告)号：US06727109B2
公开(公告)日：2004-04-27
申请号：US10210668
申请日：2002-07-31
申请人： Young Gu Ju , Won Seok Han , O Kyun Kwon , Jae Heon Shin , Byueng Su Yoo , Jung Rae Ro
发明人： Young Gu Ju , Won Seok Han , O Kyun Kwon , Jae Heon Shin , Byueng Su Yoo , Jung Rae Ro
IPC分类号： H01L2100
CPC分类号： H01S5/18308 , H01L33/145 , H01S5/02461 , H01S5/0421 , H01S5/18341 , H01S5/18369 , H01S5/2063
摘要： The present invention relates to a method of fabricating vertical-cavity surface emitting lasers being watched as a light source for long wavelength communication. The present invention includes forming a layer having a high resistance near the surface by implanting heavy ions such as silicon (Si), so that the minimum current injection diameter is made very smaller unlike implantation of a proton. Further, the present invention includes regrowing crystal so that current can flow the epi surface in parallel to significantly reduce the resistance up to the current injection part formed by silicon (Si) ions. Therefore, the present invention can not only effectively reduce the current injection diameter but also significantly reduce the resistance of a device to reduce generation of a heat. Further, the present invention can further improve dispersion of a heat using InP upon regrowth and thus improve the entire performance of the device.
摘要翻译：本发明涉及一种垂直腔表面发射激光器的制造方法，该激光器被视为用于长波长通信的光源。本发明包括通过注入诸如硅（Si）的重离子在表面附近形成具有高电阻的层，使得最小电流注入直径不像植入质子那样非常小。此外，本发明包括再生晶体，使得电流可以平行地流动外延表面，以显着降低直到由硅（Si）离子形成的电流注入部分的电阻。因此，本发明不仅可以有效地降低电流注入直径，而且可以显着降低器件的电阻以减少发热。此外，本发明可以进一步改善在再生后使用InP的散热分散，从而提高装置的整体性能。

9. 发明申请

US20100019239A1 METHOD OF FABRICATING ZTO THIN FILM, THIN FILM TRANSISTOR EMPLOYING THE SAME, AND METHOD OF FABRICATING THIN FILM TRANSISTOR 审中-公开
标题翻译：制造ZTO薄膜的方法，使用该薄膜的薄膜晶体管以及制造薄膜晶体管的方法
公开(公告)号：US20100019239A1
公开(公告)日：2010-01-28
申请号：US12359149
申请日：2009-01-23
申请人： Woo Seok Cheong , Sung Min Yoon , Jae Heon Shin , Chi Sun Hwang
发明人： Woo Seok Cheong , Sung Min Yoon , Jae Heon Shin , Chi Sun Hwang
IPC分类号： H01L29/786 , H01L21/20
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02592 , H01L21/02631
摘要： Provided are a method of fabricating a zinc-tin-oxide (ZTO) thin film, a thin film transistor employing the same, and a method of fabricating a thin film transistor. The method of fabricating a ZTO thin film includes depositing zinc oxide and tin oxide at a deposition temperature of 450° C. or lower so that a zinc-to-tin atomic ratio is 4:1 or greater, to form an amorphous ZTO thin film. In the thin film transistor, the ZTO thin film is used as a channel layer.
摘要翻译：提供了制造锌 - 锡氧化物（ZTO）薄膜的方法，采用该方法的薄膜晶体管以及制造薄膜晶体管的方法。制造ZTO薄膜的方法包括在450℃或更低的沉积温度下沉积氧化锌和氧化锡，使得锌 - 锡原子比为4:1或更大，以形成无定形ZTO薄膜。在薄膜晶体管中，ZTO薄膜用作沟道层。

10. 发明授权

US06475818B1 Method for fabricating multi-channel array optical device 有权
标题翻译：制造多通道阵列光学器件的方法
公开(公告)号：US06475818B1
公开(公告)日：2002-11-05
申请号：US09498507
申请日：2000-02-04
申请人： O Kyun Kwon , Byueng Su Yoo , Jae Heon Shin , Jong Heob Baek
发明人： O Kyun Kwon , Byueng Su Yoo , Jae Heon Shin , Jong Heob Baek
IPC分类号： G01R3126
CPC分类号： H01L27/1443 , H01L27/1462 , H01L27/14625 , H01L31/0232 , Y10S438/942
摘要： A method for fabricating a multi-channel array optical device having uniform spacing between different wavelengths and for having precise wavelengths by accomplishing wavelength adjustment and by the forming of mirror layers simultaneously through a multi-layer binary mask and a selective oxidization process. This method is especially useful for fabricating multi-channel array optical devices including multi-channel passive filters and multi-channel surface emitting laser arrays. The method includes forming a plurality of semiconductor mirror layers on a semiconductor substrate; forming an oxidization protective layer on the plurality of semiconductor mirror layers; selectively removing the oxidization protective layer by using a binary mask to expose the semiconductor mirror layer which will adjust a wavelength; oxidizing the exposed semiconductor mirror layer.
摘要翻译：一种通过实现波长调整和通过多层二进制掩模和选择性氧化过程同时形成镜层来制造具有不同波长之间具有均匀间隔并且具有精确波长的多通道阵列光学器件的方法。该方法对于制造包括多通道无源滤波器和多通道表面发射激光器阵列的多通道阵列光学器件尤其有用。该方法包括在半导体衬底上形成多个半导体镜层; 在所述多个半导体镜层上形成氧化保护层; 通过使用二元掩模选择性地去除氧化保护层以暴露将调节波长的半导体镜层; 氧化暴露的半导体镜层。

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