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1. 发明授权

US07981735B2 Method of manufacturing a Schottky barrier tunnel transistor 失效
标题翻译：制造肖特基势垒隧道晶体管的方法
公开(公告)号：US07981735B2
公开(公告)日：2011-07-19
申请号：US12434779
申请日：2009-05-04
申请人： Yark Yeon Kim , Seong Jae Lee , Moon Gyu Jang , Chel Jong Choi , Myung Sim Jun , Byoung Chul Park
发明人： Yark Yeon Kim , Seong Jae Lee , Moon Gyu Jang , Chel Jong Choi , Myung Sim Jun , Byoung Chul Park
IPC分类号： H01L21/336
CPC分类号： H01L29/47 , H01L29/458 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/7839
摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.
摘要翻译：提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道来最小化对肖特基势垒隧道晶体管的栅极侧壁的损坏所造成的漏电流屏障。该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

2. 发明授权

US07745316B2 Method for fabricating Schottky barrier tunnel transistor 失效
标题翻译：制造肖特基势垒隧道晶体管的方法
公开(公告)号：US07745316B2
公开(公告)日：2010-06-29
申请号：US11930902
申请日：2007-10-31
申请人： Yark-Yeon Kim , Seong-Jae Lee , Moon-Gyu Jang , Tae-Youb Kim , Chel-Jong Choi , Myung-Sim Jun , Byoung-Chul Park
发明人： Yark-Yeon Kim , Seong-Jae Lee , Moon-Gyu Jang , Tae-Youb Kim , Chel-Jong Choi , Myung-Sim Jun , Byoung-Chul Park
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L29/78618 , H01L29/7839
摘要： Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.
摘要翻译：提供一种用于制造肖特基势垒隧道晶体管（SBTT）的方法，其可以从根本上防止由栅极电极的两个侧壁上形成的间隔物的损坏引起的栅极漏电流的产生。一种制造肖特基势垒隧道晶体管的方法，包括：a）在由支撑衬底支撑的掩埋氧化物层上形成硅图案和牺牲图案; b）在暴露于硅图案的两侧的掩埋氧化物层上形成源极/漏极区域，源极/漏极区域由金属层形成并与硅图案的两个侧壁接触; c）去除牺牲图案以暴露硅图案的顶表面; 以及d）在暴露的硅图案上形成栅极绝缘层和栅电极。

3. 发明申请

US20090215232A1 SCHOTTKY BARRIER TUNNEL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：肖特基BARRIER隧道晶体管及其制造方法
公开(公告)号：US20090215232A1
公开(公告)日：2009-08-27
申请号：US12434779
申请日：2009-05-04
申请人： Yark Yeon KIM , Seong Jae LEE , Moon Gyu JANG , Chel Jong CHOI , Myung Sim JUN , Byoung Chul PARK
发明人： Yark Yeon KIM , Seong Jae LEE , Moon Gyu JANG , Chel Jong CHOI , Myung Sim JUN , Byoung Chul PARK
IPC分类号： H01L21/338
CPC分类号： H01L29/47 , H01L29/458 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/7839
摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.
摘要翻译：提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道来最小化对肖特基势垒隧道晶体管的栅极侧壁的损坏所造成的漏电流屏障。该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

4. 发明授权

US07545000B2 Schottky barrier tunnel transistor and method of manufacturing the same 有权
标题翻译：肖特基势垒隧道晶体管及其制造方法
公开(公告)号：US07545000B2
公开(公告)日：2009-06-09
申请号：US11485837
申请日：2006-07-13
申请人： Yark Yeon Kim , Seong Jae Lee , Moon Gyu Jang , Chel Jong Choi , Myung Sim Jun , Byoung Chul Park
发明人： Yark Yeon Kim , Seong Jae Lee , Moon Gyu Jang , Chel Jong Choi , Myung Sim Jun , Byoung Chul Park
IPC分类号： H01L27/01
CPC分类号： H01L29/47 , H01L29/458 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/7839
摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.
摘要翻译：提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道，将肖特基势垒隧道晶体管的栅极侧壁损坏所造成的漏电流减到最小屏障。该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

5. 发明申请

US20080132049A1 METHOD FOR FABRICATING SCHOTTKY BARRIER TUNNEL TRANSISTOR 失效
标题翻译：用于制作肖特基栅栏隧道晶体管的方法
公开(公告)号：US20080132049A1
公开(公告)日：2008-06-05
申请号：US11930902
申请日：2007-10-31
申请人： Yark-Yeon KIM , Seong-Jae Lee , Moon-Gyu Jang , Tae-Youb Kim , Chel-Jong Choi , Myung-Sim Jun , Byoung-Chul Park
发明人： Yark-Yeon KIM , Seong-Jae Lee , Moon-Gyu Jang , Tae-Youb Kim , Chel-Jong Choi , Myung-Sim Jun , Byoung-Chul Park
IPC分类号： H01L21/334
CPC分类号： H01L29/78618 , H01L29/7839
摘要： Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.
摘要翻译：提供一种用于制造肖特基势垒隧道晶体管（SBTT）的方法，其可以从根本上防止由栅极电极的两个侧壁上形成的间隔物的损坏引起的栅极漏电流的产生。一种制造肖特基势垒隧道晶体管的方法，包括：a）在由支撑衬底支撑的掩埋氧化物层上形成硅图案和牺牲图案; b）在暴露于硅图案的两侧的掩埋氧化物层上形成源极/漏极区域，源极/漏极区域由金属层形成并与硅图案的两个侧壁接触; c）去除牺牲图案以暴露硅图案的顶表面; 以及d）在暴露的硅图案上形成栅极绝缘层和栅电极。

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