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1. 发明授权

US07981735B2 Method of manufacturing a Schottky barrier tunnel transistor 失效
标题翻译：制造肖特基势垒隧道晶体管的方法
公开(公告)号：US07981735B2
公开(公告)日：2011-07-19
申请号：US12434779
申请日：2009-05-04
申请人： Yark Yeon Kim , Seong Jae Lee , Moon Gyu Jang , Chel Jong Choi , Myung Sim Jun , Byoung Chul Park
发明人： Yark Yeon Kim , Seong Jae Lee , Moon Gyu Jang , Chel Jong Choi , Myung Sim Jun , Byoung Chul Park
IPC分类号： H01L21/336
CPC分类号： H01L29/47 , H01L29/458 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/7839
摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.
摘要翻译：提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道来最小化对肖特基势垒隧道晶体管的栅极侧壁的损坏所造成的漏电流屏障。该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

2. 发明授权

US07545000B2 Schottky barrier tunnel transistor and method of manufacturing the same 有权
标题翻译：肖特基势垒隧道晶体管及其制造方法
公开(公告)号：US07545000B2
公开(公告)日：2009-06-09
申请号：US11485837
申请日：2006-07-13
申请人： Yark Yeon Kim , Seong Jae Lee , Moon Gyu Jang , Chel Jong Choi , Myung Sim Jun , Byoung Chul Park
发明人： Yark Yeon Kim , Seong Jae Lee , Moon Gyu Jang , Chel Jong Choi , Myung Sim Jun , Byoung Chul Park
IPC分类号： H01L27/01
CPC分类号： H01L29/47 , H01L29/458 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/7839
摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.
摘要翻译：提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道，将肖特基势垒隧道晶体管的栅极侧壁损坏所造成的漏电流减到最小屏障。该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

3. 发明授权

US07713826B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07713826B2
公开(公告)日：2010-05-11
申请号：US12045797
申请日：2008-03-11
申请人： Chel Jong Choi , Moon Gyu Jang , Yark Yeon Kim , Myung Sim Jun , Tae Youb Kim
发明人： Chel Jong Choi , Moon Gyu Jang , Yark Yeon Kim , Myung Sim Jun , Tae Youb Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/28229 , H01L21/28079 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： Provided is a method of manufacturing a semiconductor device including a high-k dielectric thin layer formed using an interfacial reaction. The method includes the steps of: forming an oxide layer on a silicon substrate; depositing a metal layer on the oxide layer to form a metal silicate layer using an interfacial reaction between the oxide layer and the metal layer; forming a metal gate by etching the metal silicate layer and the metal layer; and forming a lightly doped drain (LDD) region and source and drain regions in the silicon substrate after forming the metal gate. In this method, a semiconductor device having high quality and performance can be manufactured by a simpler process at lower cost.
摘要翻译：提供一种制造包括使用界面反应形成的高k电介质薄层的半导体器件的方法。该方法包括以下步骤：在硅衬底上形成氧化物层; 使用氧化物层和金属层之间的界面反应，在氧化物层上沉积金属层以形成金属硅酸盐层; 通过蚀刻金属硅酸盐层和金属层形成金属栅极; 以及在形成金属栅极之后在硅衬底中形成轻掺杂漏极（LDD）区域和源极和漏极区域。在该方法中，可以通过更简单的工艺以较低的成本制造具有高品质和高性能的半导体器件。

4. 发明申请

US20080299736A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20080299736A1
公开(公告)日：2008-12-04
申请号：US12045797
申请日：2008-03-11
申请人： Chel Jong Choi , Moon Gyu Jang , Yark Yeon Kim , Myung Sim Jun , Tae Youb Kim
发明人： Chel Jong Choi , Moon Gyu Jang , Yark Yeon Kim , Myung Sim Jun , Tae Youb Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/28229 , H01L21/28079 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： Provided is a method of manufacturing a semiconductor device including a high-k dielectric thin layer formed using an interfacial reaction. The method includes the steps of: forming an oxide layer on a silicon substrate; depositing a metal layer on the oxide layer to form a metal silicate layer using an interfacial reaction between the oxide layer and the metal layer; forming a metal gate by etching the metal silicate layer and the metal layer; and forming a lightly doped drain (LDD) region and source and drain regions in the silicon substrate after forming the metal gate. In this method, a semiconductor device having high quality and performance can be manufactured by a simpler process at lower cost.
摘要翻译：提供一种制造包括使用界面反应形成的高k电介质薄层的半导体器件的方法。该方法包括以下步骤：在硅衬底上形成氧化物层; 使用氧化物层和金属层之间的界面反应，在氧化物层上沉积金属层以形成金属硅酸盐层; 通过蚀刻金属硅酸盐层和金属层形成金属栅极; 以及在形成金属栅极之后在硅衬底中形成轻掺杂漏极（LDD）区域和源极和漏极区域。在该方法中，可以通过更简单的工艺以较低的成本制造具有高品质和高性能的半导体器件。

5. 发明授权

US07605065B2 Schottky barrier tunnel single electron transistor and method of manufacturing the same 有权
标题翻译：肖特基势垒隧道单电子晶体管及其制造方法
公开(公告)号：US07605065B2
公开(公告)日：2009-10-20
申请号：US11839704
申请日：2007-08-16
申请人： Moon Gyu Jang , Yark Yeon Kim , Jae Heon Shin , Seong Jae Lee
发明人： Moon Gyu Jang , Yark Yeon Kim , Jae Heon Shin , Seong Jae Lee
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/872
摘要： Provided are a Schottky barrier tunnel single electron transistor and a method of manufacturing the same that use a Schottky barrier formed between metal and semiconductor by replacing a source and a drain with silicide as a reactant of silicon and metal, instead of a conventional method of manufacturing a single electron transistor (SET) that includes source and drain regions by implanting dopants such that an artificial quantum dot is formed in a channel region. As a result, it does not require a conventional PADOX process to form a quantum dot for a single electron transistor (SET), height and width of a tunneling barrier can be artificially adjusted by using silicide materials that have various Schottky junction barriers, and it is possible to improve current driving capability of the single electron transistor (SET).
摘要翻译：提供了一种肖特基势垒隧道单电子晶体管及其制造方法，其替代传统的制造方法，而是用硅化物替代源极和漏极作为硅和金属的反应物，从而形成金属和半导体之间形成的肖特基势垒单电子晶体管（SET），其通过注入掺杂剂而包括源极和漏极区域，使得在沟道区域中形成人造量子点。结果，不需要传统的PADOX工艺来形成单电子晶体管（SET）的量子点，隧道势垒的高度和宽度可以通过使用具有各种肖特基结屏障的硅化物材料进行人工调整，而且可以提高单电子晶体管（SET）的电流驱动能力。

6. 发明授权

US07566642B2 Process of manufacturing an N-type Schottky barrier tunnel transistor 有权
标题翻译：制造N型肖特基势垒隧道晶体管的工艺
公开(公告)号：US07566642B2
公开(公告)日：2009-07-28
申请号：US11188076
申请日：2005-07-22
申请人： Yark Yeon Kim , Moon Gyu Jang , Jae Heon Shin , Seong Jae Lee
发明人： Yark Yeon Kim , Moon Gyu Jang , Jae Heon Shin , Seong Jae Lee
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/2252 , H01L21/2254 , H01L21/28518 , H01L21/28537 , H01L29/458 , H01L29/4908 , H01L29/66636 , H01L29/7834 , H01L29/7839
摘要： An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.
摘要翻译：提供了n型SBTT及其制造方法。 SBTT包括硅层，栅极，具有稀土金属硅化物层和过渡金属硅化物层的双层。硅层具有沟道区。栅极以重叠的方式形成在沟道区上，并且在其相对于硅层的界面上具有栅极介电层。双层形成为具有介于硅层之间的沟道区的源极/漏极。

7. 发明申请

US20090250756A1 N-TYPE SCHOTTKY BARRIER TUNNEL TRANSISTOR AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译： N型肖特基隧道式隧道式晶体管及其制造方法
公开(公告)号：US20090250756A1
公开(公告)日：2009-10-08
申请号：US12485777
申请日：2009-06-16
申请人： Yark Yeon Kim , Moon Gyu Jang , Jae Heon Shin , Seong Jae Lee
发明人： Yark Yeon Kim , Moon Gyu Jang , Jae Heon Shin , Seong Jae Lee
IPC分类号： H01L27/12
CPC分类号： H01L29/665 , H01L21/2252 , H01L21/2254 , H01L21/28518 , H01L21/28537 , H01L29/458 , H01L29/4908 , H01L29/66636 , H01L29/7834 , H01L29/7839
摘要： An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.
摘要翻译：提供了n型SBTT及其制造方法。 SBTT包括硅层，栅极，具有稀土金属硅化物层和过渡金属硅化物层的双层。硅层具有沟道区。栅极以重叠的方式形成在沟道区上，并且在其相对于硅层的界面上具有栅极介电层。双层形成为具有介于硅层之间的沟道区的源极/漏极。

8. 发明授权

US07312510B2 Device using ambipolar transport in SB-MOSFET and method for operating the same 失效
标题翻译：在SB-MOSFET中使用双极传输的器件及其操作方法
公开(公告)号：US07312510B2
公开(公告)日：2007-12-25
申请号：US11187654
申请日：2005-07-22
申请人： Jae Heon Shin , Moon Gyu Jang , Yark Yeon Kim , Seong Jae Lee
发明人： Jae Heon Shin , Moon Gyu Jang , Yark Yeon Kim , Seong Jae Lee
IPC分类号： H01L29/47
CPC分类号： H01L29/7839 , G11C11/56
摘要： A device using an ambipolar transport of an SB-MOSFET and a method for operating the same are provided. The SB-MOSFET includes: a silicon channel region; a source and a drain contacted on both sides of the channel region and formed of material including metal layer; and a gate formed on the channel region, with a gate dielectric layer interposed therebetween. Positive (+), 0 or negative (−) gate voltage is selectively applied to the gate, the channel becomes off-state when the gate voltage between a negative threshold voltage and a positive threshold voltage is applied, and the channel becomes a first on-state and a second on-state when the gate voltage is lower than the negative threshold voltage or higher than the positive threshold voltage. Accordingly, it is possible to implement three current states, that is, hole current, electron current, and no current. The SB-MOSFET can be applied to a multi-bit memory and/or multi-bit logic device.
摘要翻译：提供了使用SB-MOSFET的双极运输的装置及其操作方法。 SB-MOSFET包括：硅沟道区; 源极和漏极在沟道区域的两侧接触并由包括金属层的材料形成; 以及形成在沟道区上的栅极，介于其间的栅介质层。正极（+），0或负（ - ）栅极电压选择性地施加到栅极，当施加负阈值电压和正阈值电压之间的栅极电压时，通道变为截止状态，并且通道变为第一个当门电压低于负阈值电压或高于正阈值电压时，状态和第二导通状态。因此，可以实现三种电流状态，即空穴电流，电子电流，无电流。 SB-MOSFET可以应用于多位存储器和/或多位逻辑器件。

9. 发明授权

US07268407B2 Schottky barrier tunnel single electron transistor and method of manufacturing the same 失效
标题翻译：肖特基势垒隧道单电子晶体管及其制造方法
公开(公告)号：US07268407B2
公开(公告)日：2007-09-11
申请号：US11196180
申请日：2005-08-03
申请人： Moon Gyu Jang , Yark Yeon Kim , Jae Heon Shin , Seong Jae Lee
发明人： Moon Gyu Jang , Yark Yeon Kim , Jae Heon Shin , Seong Jae Lee
IPC分类号： H01L31/07
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/872
摘要： Provided are a Schottky barrier tunnel single electron transistor and a method of manufacturing the same that use a Schottky barrier formed between metal and semiconductor by replacing a source and a drain with silicide as a reactant of silicon and metal, instead of a conventional method of manufacturing a single electron transistor (SET) that includes source and drain regions by implanting dopants such that an artificial quantum dot is formed in a channel region. As a result, it does not require a conventional PADOX process to form a quantum dot for a single electron transistor (SET), height and width of a tunneling barrier can be artificially adjusted by using silicide materials that have various Schottky junction barriers, and it is possible to improve current driving capability of the single electron transistor (SET).
摘要翻译：提供了一种肖特基势垒隧道单电子晶体管及其制造方法，其替代传统的制造方法，而是用硅化物替代源极和漏极作为硅和金属的反应物，从而形成金属和半导体之间形成的肖特基势垒单电子晶体管（SET），其通过注入掺杂剂而包括源极和漏极区域，使得在沟道区域中形成人造量子点。结果，不需要传统的PADOX工艺来形成单电子晶体管（SET）的量子点，隧道势垒的高度和宽度可以通过使用具有各种肖特基结屏障的硅化物材料进行人工调整，而且可以提高单电子晶体管（SET）的电流驱动能力。

10. 发明申请

US20110192439A1 THERMOELECTRIC ARRAY 审中-公开
标题翻译：热电阵列
公开(公告)号：US20110192439A1
公开(公告)日：2011-08-11
申请号：US13022251
申请日：2011-02-07
申请人： Young Sam PARK , Moon Gyu Jang , Myung Sim Jun , Young Hoon Hyun
发明人： Young Sam PARK , Moon Gyu Jang , Myung Sim Jun , Young Hoon Hyun
IPC分类号： H01L35/30
CPC分类号： H01L35/30
摘要： Provided is a thermoelectric array including a plurality of thermoelectric elements arranged in m rows and n columns (each of m and n is an integer equal to or more than 1), each thermoelectric element including a heat absorption layer, a first heat sink layer, a second heat sink layer, a first-conductivity-type leg, and a second-conductivity-type leg formed on the same plane. The heat absorption layers of the thermoelectric elements adjacently disposed in a row or column direction are disposed adjacent to each other, and the first and second heat sink layers of the adjacent thermoelectric elements are disposed adjacent to each other. In this case, thermal interference between adjacent thermoelectric elements may be minimized, thereby obtaining a thermoelectric array having a high figure of merit.
摘要翻译：本发明提供一种热电阵列，其包括以m行n列（m和n为1以上的整数）排列的多个热电元件，热电元件包括吸热层，第1散热层，第二散热层，第一导电型脚和形成在同一平面上的第二导电型脚。相邻地配置在行或列方向上的热电元件的吸热层相邻配置，相邻的热电元件的第一和第二散热层相邻配置。在这种情况下，相邻热电元件之间的热干扰可以最小化，从而获得具有高品质因数的热电阵列。

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