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1. 发明授权

US08952458B2 Gate dielectric layer having interfacial layer and high-K dielectric over the interfacial layer 有权
标题翻译：栅介质层在界面层上具有界面层和高K电介质
公开(公告)号：US08952458B2
公开(公告)日：2015-02-10
申请号：US13086491
申请日：2011-04-14
申请人： Wei-Yang Lee , Xiong-Fei Yu , Da-Yuan Lee , Kuang-Yuan Hsu
发明人： Wei-Yang Lee , Xiong-Fei Yu , Da-Yuan Lee , Kuang-Yuan Hsu
IPC分类号： H01L21/70 , H01L21/02 , H01L21/8238 , H01L29/423 , H01L21/28 , H01L29/51 , H01L29/66
CPC分类号： H01L29/66477 , H01L21/28185 , H01L21/823857 , H01L29/42368 , H01L29/513 , H01L29/66545
摘要： A semiconductor device includes a substrate having a first active region, a first gate structure over the first active region, wherein the first gate structure includes a first interfacial layer having a convex top surface, a first high-k dielectric over the first interfacial layer, and a first gate electrode over the first high-k dielectric.
摘要翻译：一种半导体器件包括具有第一有源区，第一有源区上的第一栅结构的衬底，其中第一栅结构包括具有凸顶表面的第一界面层，第一界面层上的第一高k电介质，以及在第一高k电介质上的第一栅电极。

2. 发明申请

US20130102142A1 STRESS MODULATION FOR METAL GATE SEMICONDUCTOR DEVICE 有权
标题翻译：金属栅极半导体器件的应力调制
公开(公告)号：US20130102142A1
公开(公告)日：2013-04-25
申请号：US13278725
申请日：2011-10-21
申请人： Wei-Yang Lee , Meng-Hsuan Chan , Huang Ching Yu , Da-Yuan Lee , Kuang-Yuan Hsu
发明人： Wei-Yang Lee , Meng-Hsuan Chan , Huang Ching Yu , Da-Yuan Lee , Kuang-Yuan Hsu
IPC分类号： H01L21/28
CPC分类号： H01L21/265 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L29/513 , H01L29/66545 , H01L29/78 , H01L29/7843 , H01L29/7845
摘要： The present disclosure provides a method of semiconductor device fabrication including removing a sacrificial gate structure formed on a substrate to provide an opening. A metal gate structure is then formed in the opening. The forming of the metal gate structure includes forming a first layer (including metal) on a gate dielectric layer, wherein the first layer includes a metal and performing a stress modulation process on the first layer. The stress modulation process may include ion implantation of a neutral species such as silicon, argon, germanium, and xenon.
摘要翻译：本公开提供了一种半导体器件制造方法，包括去除形成在衬底上的牺牲栅极结构以提供开口。然后在开口中形成金属栅极结构。金属栅极结构的形成包括在栅极介电层上形成第一层（包括金属），其中第一层包括金属并在第一层上执行应力调制过程。应力调制过程可以包括中性物质如硅，氩，锗和氙的离子注入。

3. 发明申请

US20120264281A1 METHOD OF FABRICATING A PLURALITY OF GATE STRUCTURES 有权
标题翻译：制造大量门结构的方法
公开(公告)号：US20120264281A1
公开(公告)日：2012-10-18
申请号：US13085029
申请日：2011-04-12
申请人： Jian-Hao CHEN , Wei-Yang LEE , Wei-Yeh TANG , Xiong-Fei YU , Kuang-Yuan HSU
发明人： Jian-Hao CHEN , Wei-Yang LEE , Wei-Yeh TANG , Xiong-Fei YU , Kuang-Yuan HSU
IPC分类号： H01L21/28
CPC分类号： H01L29/6659 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/0228 , H01L21/32139 , H01L21/823437 , H01L21/823828 , H01L29/66545 , H01L29/7833
摘要： The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode.
摘要翻译：本发明涉及集成电路制造，更具体地涉及具有多个栅极结构的半导体器件。制造多个栅极结构的示例性方法包括提供硅衬底; 在衬底上沉积虚拟氧化物层; 在虚拟氧化物层上沉积虚拟栅电极层; 图案化层以限定多个虚拟门; 在所述多个虚拟栅极上形成含氮侧壁间隔物; 在所述含氮侧壁间隔件之间形成层间电介质层; 通过原子层沉积（ALD）工艺在层间介质层上选择性地沉积硬掩模层; 去除所述伪栅电极层; 去除虚拟氧化物层; 沉积栅极电介质; 并沉积栅电极。

4. 发明授权

US08283222B2 Method to form a semiconductor device having gate dielectric layers of varying thickness 有权
标题翻译：形成具有不同厚度的栅极电介质层的半导体器件的方法
公开(公告)号：US08283222B2
公开(公告)日：2012-10-09
申请号：US13215658
申请日：2011-08-23
申请人： Kuang-Yuan Hsu , Da-Yuan Lee , Wei-Yang Lee , Hun-Jan Tao
发明人： Kuang-Yuan Hsu , Da-Yuan Lee , Wei-Yang Lee , Hun-Jan Tao
IPC分类号： H01L21/338
CPC分类号： H01L21/823857 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L29/513 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method for fabricating an integrated circuit device is disclosed which includes providing a substrate having first, second, and third regions; and forming first, second, and third gate structures in the first, second, and third regions, respectively. The first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure. Forming the gate dielectric layer of the first, second, and third thicknesses can include forming an etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions while forming the first, second, and third gate structures, and/or prior to forming the gate dielectric layer in at least one of the first, second, or third regions, performing an implantation process on the at least one region.
摘要翻译：公开了一种用于制造集成电路器件的方法，其包括提供具有第一，第二和第三区域的衬底; 以及分别在第一，第二和第三区域中形成第一，第二和第三栅极结构。第一，第二和第三栅极结构包括栅极介电层，栅极电介质层是第一栅极结构中的第一厚度，第二栅极结构中的第二厚度，以及第三栅极结构中的第三厚度。形成第一，第二和第三厚度的栅介质层可以包括在形成第一，第二和第三栅极结构的至少一个第一，第二或第三区域中的栅极电介质层上方形成蚀刻阻挡层，和/或在第一，第二或第三区域中的至少一个中形成栅介质层之前，在至少一个区域上执行注入工艺。

5. 发明申请

US20120049247A1 MODIFIED PROFILE GATE STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FORMING THEREOF 有权
标题翻译：半导体器件的改性型材结构及其形成方法
公开(公告)号：US20120049247A1
公开(公告)日：2012-03-01
申请号：US12872642
申请日：2010-08-31
申请人： Da-Yuan Lee , Kuang-Yuan Hsu , Matt Yeh , Yi-Chen Huang , Fan-Yi Hsu , Hui Ouyang , Ming-Jie Huang , Shin Hsien Liao
发明人： Da-Yuan Lee , Kuang-Yuan Hsu , Matt Yeh , Yi-Chen Huang , Fan-Yi Hsu , Hui Ouyang , Ming-Jie Huang , Shin Hsien Liao
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28114 , H01L29/42376 , H01L29/495 , H01L29/4966 , H01L29/6656
摘要： A method of fabricating a semiconductor device is illustrated. A modified profile opening is formed on a substrate. The modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate. The second width is greater than the first width. A metal gate electrode is formed by filling the modified profile opening with a conductive material. A semiconductor device is also described, the device having a metal gate structure with a first width and a second, differing, width.
摘要翻译：示出了制造半导体器件的方法。改进的型材开口形成在基板上。改进的型材开口包括靠近基材的表面的第一宽度和与基材相对的第二宽度。第二宽度大于第一宽度。通过用导电材料填充改性型材开口形成金属栅电极。还描述了一种半导体器件，该器件具有第一宽度和第二宽度不同的金属栅极结构。

6. 发明授权

US08048810B2 Method for metal gate N/P patterning 有权
标题翻译：金属栅极N / P图案化方法
公开(公告)号：US08048810B2
公开(公告)日：2011-11-01
申请号：US12696252
申请日：2010-01-29
申请人： Fang Wen Tsai , Jim Cy Huang , Shun Wu Lin , Li-Shiun Chen , Kuang-Yuan Hsu
发明人： Fang Wen Tsai , Jim Cy Huang , Shun Wu Lin , Li-Shiun Chen , Kuang-Yuan Hsu
IPC分类号： H01L2/311
CPC分类号： G03F7/20 , H01L21/28
摘要： A method for fabricating a integrated circuit is disclosed. An exemplary method includes providing a substrate; forming a hard mask layer over the substrate; forming a patterned photoresist layer over the hard mask layer, such that portions of the hard mask layer are exposed; performing a dry etching process to remove the exposed portions of the hard mask layer; removing the patterned photoresist layer using at least one of a nitrogen plasma ashing and a hydrogen plasma ashing; and performing a wet etching process to remove remaining portions of the hard mask layer.
摘要翻译：公开了一种用于制造集成电路的方法。一种示例性方法包括提供基底; 在衬底上形成硬掩模层; 在所述硬掩模层上形成图案化的光致抗蚀剂层，使得所述硬掩模层的部分被暴露; 执行干蚀刻工艺以去除硬掩模层的暴露部分; 使用氮等离子体灰化和氢等离子体灰化中的至少一种去除图案化的光致抗蚀剂层; 并进行湿式蚀刻处理以去除硬掩模层的剩余部分。

7. 发明申请

US20110193180A1 METHOD AND APPARATUS OF FORMING A GATE 有权
标题翻译：形成门的方法和装置
公开(公告)号：US20110193180A1
公开(公告)日：2011-08-11
申请号：US12700901
申请日：2010-02-05
申请人： Jian-Hao Chen , Da-Yuan Lee , Kuang-Yuan Hsu
发明人： Jian-Hao Chen , Da-Yuan Lee , Kuang-Yuan Hsu
IPC分类号： H01L29/51 , H01L21/283
CPC分类号： H01L21/28194 , H01L21/02148 , H01L21/02181 , H01L21/022 , H01L21/0228 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665
摘要： The present disclosure provides an apparatus that includes a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a first gate dielectric layer that is disposed over the substrate. The first gate dielectric layer includes a first material. The first gate dielectric layer has a first thickness that is less than a threshold thickness at which a portion of the first material of the first gate dielectric layer begins to crystallize. The semiconductor device also includes a second gate dielectric layer that is disposed over the first gate dielectric layer. The second gate dielectric layer includes a second material that is different from the first material. The second gate dielectric layer has a second thickness that is less than a threshold thickness at which a portion of the second material of the second gate dielectric layer begins to crystallize.
摘要翻译：本公开提供了一种包括半导体器件的装置。半导体器件包括衬底。半导体器件还包括设置在衬底上的第一栅极电介质层。第一栅介质层包括第一材料。第一栅极介电层具有小于第一栅极电介质层的第一材料的一部分开始结晶的阈值厚度的第一厚度。半导体器件还包括设置在第一栅极介电层上的第二栅极电介质层。第二栅极介电层包括与第一材料不同的第二材料。第二栅极电介质层具有小于第二栅极电介质层的第二材料的一部分开始结晶的阈值厚度的第二厚度。

8. 发明申请

US20110189847A1 METHOD FOR METAL GATE N/P PATTERNING 有权
标题翻译：金属门N / P图案的方法
公开(公告)号：US20110189847A1
公开(公告)日：2011-08-04
申请号：US12696252
申请日：2010-01-29
申请人： Fang Wen Tsai , Jim C.Y. Huang , Shun Wu Lin , Li-Shiun Chen , Kuang-Yuan Hsu
发明人： Fang Wen Tsai , Jim C.Y. Huang , Shun Wu Lin , Li-Shiun Chen , Kuang-Yuan Hsu
IPC分类号： H01L21/28 , G03F7/20
CPC分类号： G03F7/20 , H01L21/28
摘要： A method for fabricating a integrated circuit is disclosed. An exemplary method includes providing a substrate; forming a hard mask layer over the substrate; forming a patterned photoresist layer over the hard mask layer, such that portions of the hard mask layer are exposed; performing a dry etching process to remove the exposed portions of the hard mask layer; removing the patterned photoresist layer using at least one of a nitrogen plasma ashing and a hydrogen plasma ashing; and performing a wet etching process to remove remaining portions of the hard mask layer.
摘要翻译：公开了一种用于制造集成电路的方法。一种示例性方法包括提供基底; 在衬底上形成硬掩模层; 在所述硬掩模层上形成图案化的光致抗蚀剂层，使得所述硬掩模层的部分被暴露; 执行干蚀刻工艺以去除硬掩模层的暴露部分; 使用氮等离子体灰化和氢等离子体灰化中的至少一种去除图案化的光致抗蚀剂层; 并进行湿式蚀刻处理以去除硬掩模层的剩余部分。

9. 发明申请

US20110089484A1 METHOD AND SYSTEM FOR METAL GATE FORMATION WITH WIDER METAL GATE FILL MARGIN 有权
标题翻译：用于金属栅格形成的方法和系统，具有宽的金属栅格膜
公开(公告)号：US20110089484A1
公开(公告)日：2011-04-21
申请号：US12582031
申请日：2009-10-20
申请人： Peng-Soon Lim , Meng-Hsuan Chan , Kuang-Yuan Hsu
发明人： Peng-Soon Lim , Meng-Hsuan Chan , Kuang-Yuan Hsu
IPC分类号： H01L29/78 , H01L21/283
CPC分类号： H01L29/4236 , H01L21/28114 , H01L29/42376 , H01L29/66621
摘要： A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.
摘要翻译：一种方法包括提供具有栅极沟槽的半导体衬底，并且使用物理气相沉积（PVD）工艺在衬底上沉积金属层以部分地填充沟槽。金属层包括比底部更薄的底部部分和侧壁部分。所述方法还包括在所述金属层上形成涂层，使所述涂层回蚀刻，使得所述涂层的一部分保护所述沟槽内的所述金属层的一部分，以及去除所述金属层的未被保护的部分。不同的方面涉及一种半导体器件，其包括包括具有顶表面的沟槽的栅极和在沟槽上形成的金属层，其中金属层包括侧壁部分和底部，并且其中侧壁部分比底部。

10. 发明授权

US08952462B2 Method and apparatus of forming a gate 有权
标题翻译：形成门的方法和装置
公开(公告)号：US08952462B2
公开(公告)日：2015-02-10
申请号：US12700901
申请日：2010-02-05
申请人： Jian-Hao Chen , Da-Yuan Lee , Kuang-Yuan Hsu
发明人： Jian-Hao Chen , Da-Yuan Lee , Kuang-Yuan Hsu
IPC分类号： H01L29/94 , H01L27/108 , H01L21/02 , H01L21/28 , H01L29/51 , H01L29/49 , H01L29/66
CPC分类号： H01L21/28194 , H01L21/02148 , H01L21/02181 , H01L21/022 , H01L21/0228 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665
摘要： The present disclosure provides an apparatus that includes a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a first gate dielectric layer that is disposed over the substrate. The first gate dielectric layer includes a first material. The first gate dielectric layer has a first thickness that is less than a threshold thickness at which a portion of the first material of the first gate dielectric layer begins to crystallize. The semiconductor device also includes a second gate dielectric layer that is disposed over the first gate dielectric layer. The second gate dielectric layer includes a second material that is different from the first material. The second gate dielectric layer has a second thickness that is less than a threshold thickness at which a portion of the second material of the second gate dielectric layer begins to crystallize.
摘要翻译：本公开提供了一种包括半导体器件的装置。半导体器件包括衬底。半导体器件还包括设置在衬底上的第一栅极电介质层。第一栅介质层包括第一材料。第一栅极介电层具有小于第一栅极电介质层的第一材料的一部分开始结晶的阈值厚度的第一厚度。半导体器件还包括设置在第一栅极介电层上的第二栅极电介质层。第二栅极介电层包括与第一材料不同的第二材料。第二栅极电介质层具有小于第二栅极电介质层的第二材料的一部分开始结晶的阈值厚度的第二厚度。

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