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1. 发明授权

US07928501B2 Semiconductor device and methods of forming and operating the same 有权
标题翻译：半导体器件及其形成和操作的方法
公开(公告)号：US07928501B2
公开(公告)日：2011-04-19
申请号：US12458218
申请日：2009-07-06
申请人： Wook-Hyun Kwon , Byung-Gook Park , Yun-Heub Song , Yoon Kim
发明人： Wook-Hyun Kwon , Byung-Gook Park , Yun-Heub Song , Yoon Kim
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L29/66833 , H01L29/7923
摘要： Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.
摘要翻译：提供半导体器件以及形成和操作半导体器件的方法。半导体器件可以包括从半导体衬底延伸并且二维地设置在半导体衬底上的有源柱，在一个方向上连接有源柱的上部互连，与上部互连交叉的下部互连，并且设置在有源柱之间，跨越上部的字线互连并且布置在活动柱之间，以及布置在字线和活动柱之间的数据存储图案。

2. 发明授权

US08354708B2 Methods of forming and operating semiconductor device 有权
标题翻译：半导体器件的形成和操作方法
公开(公告)号：US08354708B2
公开(公告)日：2013-01-15
申请号：US13087643
申请日：2011-04-15
申请人： Wook-Hyun Kwon , Byung-Gook Park , Yun-Heub Song , Yoon Kim
发明人： Wook-Hyun Kwon , Byung-Gook Park , Yun-Heub Song , Yoon Kim
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L29/66833 , H01L29/7923
摘要： Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.
摘要翻译：提供半导体器件以及形成和操作半导体器件的方法。半导体器件可以包括从半导体衬底延伸并且二维地设置在半导体衬底上的有源柱，在一个方向上连接有源柱的上部互连，与上部互连交叉的下部互连，并且设置在有源柱之间，跨越上部的字线互连并且布置在活动柱之间，以及布置在字线和活动柱之间的数据存储图案。

3. 发明申请

US20100001339A1 Semiconductor device and methods of forming and operating the same 有权
标题翻译：半导体器件及其形成和操作的方法
公开(公告)号：US20100001339A1
公开(公告)日：2010-01-07
申请号：US12458218
申请日：2009-07-06
申请人： Wook-Hyun Kwon , Byung-Gook Park , Yun-Heub Song , Yoon Kim
发明人： Wook-Hyun Kwon , Byung-Gook Park , Yun-Heub Song , Yoon Kim
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L29/66833 , H01L29/7923
摘要： Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.
摘要翻译：提供半导体器件以及形成和操作半导体器件的方法。半导体器件可以包括从半导体衬底延伸并且二维地设置在半导体衬底上的有源柱，在一个方向上连接有源柱的上部互连，与上部互连交叉的下部互连，并且设置在有源柱之间，跨越上部的字线互连并且布置在活动柱之间，以及布置在字线和活动柱之间的数据存储图案。

4. 发明授权

US07045413B2 Method of manufacturing a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit manufactured thereby 有权
公开(公告)号：US07045413B2
公开(公告)日：2006-05-16
申请号：US10773805
申请日：2004-02-05
申请人： Sang-Eun Lee , Yun-Heub Song
发明人： Sang-Eun Lee , Yun-Heub Song
IPC分类号： H01L21/8238 , H01L21/00 , H01L21/84 , H01L21/8242 , H01L21/336
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/76224 , H01L27/0207 , H01L27/105 , H01L27/11526 , H01L27/11539 , H01L27/11541
摘要： Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions between the gate patterns include first spaces having a first width and second spaces having a second width greater than the first width. Spacers are formed on sidewalls of the second spaces, and spacer layer patterns filling the first spaces are also formed together with the spacers. The spacers are selectively removed to expose the sidewalls of the first spaces. As a result, the semiconductor integrated circuit includes wide spaces enlarged by the removal of the spacers and narrow and deep spaces filled with the spacer layer patterns.

5. 发明授权

US07436017B2 Semiconductor integrated circuit using a selective disposable spacer 有权
标题翻译：使用选择性一次性间隔器的半导体集成电路
公开(公告)号：US07436017B2
公开(公告)日：2008-10-14
申请号：US11331659
申请日：2006-01-12
申请人： Sang-Eun Lee , Yun-Heub Song
发明人： Sang-Eun Lee , Yun-Heub Song
IPC分类号： H01L29/94
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/76224 , H01L27/0207 , H01L27/105 , H01L27/11526 , H01L27/11539 , H01L27/11541
摘要： Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions between the gate patterns include first spaces having a first width and second spaces having a second width greater than the first width. Spacers are formed on sidewalls of the second spaces, and spacer layer patterns filling the first spaces are also formed together with the spacers. The spacers are selectively removed to expose the sidewalls of the first spaces. As a result, the semiconductor integrated circuit includes wide spaces enlarged by the removal of the spacers and narrow and deep spaces filled with the spacer layer patterns.
摘要翻译：使用选择性一次性间隔物技术制造半导体集成电路的方法和由此制造的半导体集成电路的方法：该方法包括在半导体衬底上形成多个栅极图案。栅极图案之间的间隙区域包括具有第一宽度的第一空间和具有大于第一宽度的第二宽度的第二空间。隔板形成在第二空间的侧壁上，填充第一空间的间隔层图案也与间隔件一起形成。选择性地去除间隔物以露出第一空间的侧壁。结果，半导体集成电路包括通过去除间隔物和填充有间隔层图案的狭窄和深空间而扩大的宽空间。

6. 发明授权

US08222684B2 Method of manufacturing a semiconductor integrated circuit using a selective disposal spacer technique and semiconductor integrated circuit manufactured thereby 有权
标题翻译：使用选择性处理间隔物技术制造半导体集成电路的方法和由此制造的半导体集成电路
公开(公告)号：US08222684B2
公开(公告)日：2012-07-17
申请号：US12538798
申请日：2009-08-10
申请人： Sang-Eun Lee , Yun-Heub Song
发明人： Sang-Eun Lee , Yun-Heub Song
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/76224 , H01L27/0207 , H01L27/105 , H01L27/11526 , H01L27/11539 , H01L27/11541
摘要： Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns.
摘要翻译：使用选择性一次性间隔器技术制造半导体集成电路的方法和由此制造的半导体集成电路。该方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极图案，其中在所述栅极图案之间设置比所述第一空间宽的第一空间和第二空间; 在所述第一空间下的所述半导体衬底中形成第一杂质区，并在所述第二空间下在所述半导体衬底中形成第二杂质区; 在所述栅极图案的侧壁上形成绝缘间隔物，其中所述第二杂质区域的一部分被暴露，并且所述第一杂质区域被所述绝缘间隔物覆盖; 蚀刻绝缘间隔物，其中第二杂质区域的开口宽度增大，并且其中蚀刻通过湿蚀刻工艺进行; 以及在包括栅极图案的整体结构上形成层间绝缘层。

7. 发明申请

US20060118855A1 Method of manufacturing a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit manufactured thereby 有权
标题翻译：使用选择性一次性间隔物技术制造半导体集成电路的方法和由此制造的半导体集成电路
公开(公告)号：US20060118855A1
公开(公告)日：2006-06-08
申请号：US11331659
申请日：2006-01-12
申请人： Sang-Eun Lee , Yun-Heub Song
发明人： Sang-Eun Lee , Yun-Heub Song
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/76224 , H01L27/0207 , H01L27/105 , H01L27/11526 , H01L27/11539 , H01L27/11541
摘要： Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions between the gate patterns include first spaces having a first width and second spaces having a second width greater than the first width. Spacers are formed on sidewalls of the second spaces, and spacer layer patterns filling the first spaces are also formed together with the spacers. The spacers are selectively removed to expose the sidewalls of the first spaces. As a result, the semiconductor integrated circuit includes wide spaces enlarged by the removal of the spacers and narrow and deep spaces filled with the spacer layer patterns.
摘要翻译：使用选择性一次性间隔物技术制造半导体集成电路的方法和由此制造的半导体集成电路的方法：该方法包括在半导体衬底上形成多个栅极图案。栅极图案之间的间隙区域包括具有第一宽度的第一空间和具有大于第一宽度的第二宽度的第二空间。隔板形成在第二空间的侧壁上，填充第一空间的间隔层图案也与间隔件一起形成。选择性地去除间隔物以露出第一空间的侧壁。结果，半导体集成电路包括通过去除间隔物和填充有间隔层图案的狭窄和深空间而扩大的宽空间。

8. 发明授权

US07588979B2 Method of manufacturing a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit manufactured thereby 有权
标题翻译：使用选择性一次性间隔物技术制造半导体集成电路的方法和由此制造的半导体集成电路
公开(公告)号：US07588979B2
公开(公告)日：2009-09-15
申请号：US11671438
申请日：2007-02-05
申请人： Sang-Eun Lee , Yun-Heub Song
发明人： Sang-Eun Lee , Yun-Heub Song
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/76224 , H01L27/0207 , H01L27/105 , H01L27/11526 , H01L27/11539 , H01L27/11541
摘要： Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns.
摘要翻译：使用选择性一次性间隔器技术制造半导体集成电路的方法和由此制造的半导体集成电路。该方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极图案，其中在所述栅极图案之间设置比所述第一空间宽的第一空间和第二空间; 在所述第一空间下的所述半导体衬底中形成第一杂质区，并在所述第二空间下在所述半导体衬底中形成第二杂质区; 在所述栅极图案的侧壁上形成绝缘间隔物，其中所述第二杂质区域的一部分被暴露，并且所述第一杂质区域被所述绝缘间隔物覆盖; 蚀刻绝缘间隔物，其中第二杂质区域的开口宽度增大，并且其中蚀刻通过湿蚀刻工艺进行; 以及在包括栅极图案的整体结构上形成层间绝缘层。

9. 发明授权

US06635532B2 Method for fabricating NOR type flash memory device 失效
公开(公告)号：US06635532B2
公开(公告)日：2003-10-21
申请号：US10099126
申请日：2002-03-15
申请人： Yun-Heub Song , Woon-Kyung Lee
发明人： Yun-Heub Song , Woon-Kyung Lee
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： Disclosed is a method for fabricating a NOR flash memory device where a buried common source line made of an impurity diffusion layer has an even surface or a lower step difference. The method includes forming adjacent isolation layers that define an active region there between within a semiconductor substrate. Then, a floating gate pattern is formed overlying the active region. An inter-gate dielectric film and a control gate film are sequentially formed overlying the floating gate pattern. The control gate film, the inter-gate dielectric film, and the floating gate pattern are sequentially patterned, thereby forming a plurality of word lines extending across the active region. The active region between the adjacent isolation layers and the isolation layers are removed, adjacent to one sidewall of the word lines, thereby forming a common source line region. Next, impurities are implanted into the common source line region, thereby forming a common source line made of an impurity diffusion layer.

10. 发明授权

US06507522B2 Method for erasing memory cells in a nonvolatile memory 有权
标题翻译：擦除非易失性存储器中存储单元的方法
公开(公告)号：US06507522B2
公开(公告)日：2003-01-14
申请号：US09841917
申请日：2001-04-24
申请人： Joon-Sung Lee , Chan-Jo Lee , Yun-Heub Song , Seung-Keun Lee
发明人： Joon-Sung Lee , Chan-Jo Lee , Yun-Heub Song , Seung-Keun Lee
IPC分类号： G11C1604
CPC分类号： G11C16/3477 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3468
摘要： A method for managing memory cells in a nonvolatile memory, such as a flash memory, includes detecting and intermediately programming fast-erased memory cells. All of the memory cells in a sector can then be erased.
摘要翻译：用于管理非易失性存储器（诸如闪速存储器）中的存储器单元的方法包括检测和中间编程快速擦除的存储器单元。然后可以擦除扇区中的所有存储单元。

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