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1. 发明申请

US20070268749A1 Method for operating non-volatile memory device 审中-公开
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US20070268749A1
公开(公告)日：2007-11-22
申请号：US11802282
申请日：2007-05-22
申请人： Dae-Mann Kim , Wook-Hyun Kwon , Ki-Nam Kim , Chan-Kwang Park , Sang-Pil Sim
发明人： Dae-Mann Kim , Wook-Hyun Kwon , Ki-Nam Kim , Chan-Kwang Park , Sang-Pil Sim
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0483 , G11C16/3409 , G11C16/345
摘要： A method of operating a non-volatile memory device is disclosed. The memory cell includes a channel region separating a source region and a drain region, a tunnel insulating layer, a charge storage layer, and a gate electrode formed over the channel region. The method includes applying a negative voltage to the gate electrode and applying a positive voltage to at least one of the source and drain regions to inject holes into the tunnel insulating layer and thereby remove electrons trapped in the tunnel insulating layer.
摘要翻译：公开了一种操作非易失性存储器件的方法。存储单元包括分离源极区和漏极区的沟道区，隧道绝缘层，电荷存储层和形成在沟道区上的栅电极。该方法包括向栅电极施加负电压并向源区和漏区中的至少一个施加正电压，以将空穴注入到隧道绝缘层中，从而去除俘获在隧道绝缘层中的电子。

2. 发明授权

US07586135B2 Multilevel integrated circuit devices and methods of forming the same 有权
标题翻译：多层集成电路器件及其形成方法
公开(公告)号：US07586135B2
公开(公告)日：2009-09-08
申请号：US11606569
申请日：2006-11-30
申请人： Wook-Hyun Kwon , Ki-Nam Kim , Chan-Kwang Park , Soon-Moon Jung , Sang-Pil Sim
发明人： Wook-Hyun Kwon , Ki-Nam Kim , Chan-Kwang Park , Soon-Moon Jung , Sang-Pil Sim
IPC分类号： H01L29/80
CPC分类号： H01L27/0688 , H01L21/8221
摘要： Semiconductor devices including a plurality of semiconductor layers. A plurality of transistors are on each of the semiconductor layers. The transistors include gate lines and have source regions and drain regions formed between the gate lines in the respective semiconductor layer including the transistors. The semiconductor devices further include a plurality of local source line structures. Each of the local source line structures is positioned on a corresponding one of the semiconductor layers and connects a plurality of the source regions formed on the corresponding one of the semiconductor layers. Methods of forming the semiconductor devices are also provided.
摘要翻译：包括多个半导体层的半导体器件。多个晶体管位于每个半导体层上。晶体管包括栅极线，并且在包括晶体管的相应半导体层中的栅极线之间形成源极区和漏极区。半导体器件还包括多个本地源极线结构。局部源极线结构中的每一个位于相应的一个半导体层上，并连接形成在相应一个半导体层上的多个源极区。还提供了形成半导体器件的方法。

3. 发明申请

US20070176214A1 Multilevel integrated circuit devices and methods of forming the same 有权
标题翻译：多层集成电路器件及其形成方法
公开(公告)号：US20070176214A1
公开(公告)日：2007-08-02
申请号：US11606569
申请日：2006-11-30
申请人： Wook-Hyun Kwon , Ki-Nam Kim , Chan-Kwang Park , Soon-Moon Jung , Sang-Pil Sim
发明人： Wook-Hyun Kwon , Ki-Nam Kim , Chan-Kwang Park , Soon-Moon Jung , Sang-Pil Sim
IPC分类号： H01L29/768
CPC分类号： H01L27/0688 , H01L21/8221
摘要： Semiconductor devices including a plurality of semiconductor layers. A plurality of transistors are on each of the semiconductor layers. The transistors include gate lines and have source regions and drain regions formed between the gate lines in the respective semiconductor layer including the transistors. The semiconductor devices further include a plurality of local source line structures. Each of the local source line structures is positioned on a corresponding one of the semiconductor layers and connects a plurality of the source regions formed on the corresponding one of the semiconductor layers. Methods of forming the semiconductor devices are also provided.
摘要翻译：包括多个半导体层的半导体器件。多个晶体管位于每个半导体层上。晶体管包括栅极线，并且在包括晶体管的相应半导体层中的栅极线之间形成源极区和漏极区。半导体器件还包括多个本地源极线结构。局部源极线结构中的每一个位于相应的一个半导体层上，并连接形成在相应一个半导体层上的多个源极区。还提供了形成半导体器件的方法。

4. 发明申请

US20070105309A1 Contactless nonvolatile memory device and method of forming the same 有权
公开(公告)号：US20070105309A1
公开(公告)日：2007-05-10
申请号：US11590620
申请日：2006-10-31
申请人： Wook-Hyun Kwon , Chan-Kwang Park , Sang-Pil Sim
发明人： Wook-Hyun Kwon , Chan-Kwang Park , Sang-Pil Sim
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of forming a contactless nonvolatile memory device includes preparing a semiconductor substrate including a cell array region, forming a plurality of mask patterns being parallel to each other on the semiconductor substrate in the cell array region, etching the semiconductor substrate using the mask patterns as an etch mask to form a plurality of recess regions, forming a gate insulating layer on sidewalls and bottoms of the recess regions, forming a floating gate layer on an upper surface of the semiconductor substrate to fill the recess regions, planarizing the floating gate layer to expose upper surfaces of the mask patterns and to form floating gate patterns in the recess regions, forming buried impurity diffusion regions in the semiconductor substrate under the mask patterns, forming an intergate dielectric layer, forming a control gate layer, and patterning the control gate layer, the intergate dielectric layer and the floating gate pattern to form a plurality of parallel word lines crossing the mask patterns, floating gates between the word lines and the recess regions, and an intergate dielectric pattern between the floating gates and the word lines, and to expose the recess regions and the mask patterns between word lines.

5. 发明授权

US07276415B2 Contactless nonvolatile memory device and method of forming the same 有权
标题翻译：非接触非易失性存储器件及其形成方法
公开(公告)号：US07276415B2
公开(公告)日：2007-10-02
申请号：US11590620
申请日：2006-10-31
申请人： Wook-Hyun Kwon , Chan-Kwang Park , Sang-Pil Sim
发明人： Wook-Hyun Kwon , Chan-Kwang Park , Sang-Pil Sim
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of forming a contactless nonvolatile memory device includes preparing a semiconductor substrate including a cell array region, forming a plurality of mask patterns being parallel to each other on the semiconductor substrate in the cell array region, etching the semiconductor substrate using the mask patterns as an etch mask to form a plurality of recess regions, forming a gate insulating layer on sidewalls and bottoms of the recess regions, forming a floating gate layer on an upper surface of the semiconductor substrate to fill the recess regions, planarizing the floating gate layer to expose upper surfaces of the mask patterns and to form floating gate patterns in the recess regions, forming buried impurity diffusion regions in the semiconductor substrate under the mask patterns, forming an intergate dielectric layer, forming a control gate layer, and patterning the control gate layer, the intergate dielectric layer and the floating gate pattern to form a plurality of parallel word lines crossing the mask patterns, floating gates between the word lines and the recess regions, and an intergate dielectric pattern between the floating gates and the word lines, and to expose the recess regions and the mask patterns between word lines.
摘要翻译：一种形成非接触非易失性存储器件的方法包括：制备包括单元阵列区域的半导体衬底，在单元阵列区域中的半导体衬底上形成彼此平行的多个掩模图案，使用掩模图案蚀刻半导体衬底蚀刻掩模以形成多个凹陷区域，在所述凹陷区域的侧壁和底部上形成栅极绝缘层，在所述半导体衬底的上表面上形成浮栅，以填充所述凹陷区域，将所述浮栅层平坦化为露出掩模图案的上表面并在凹陷区域中形成浮置栅极图案，在掩模图案之下的半导体衬底中形成掩埋的杂质扩散区域，形成栅间电介质层，形成控制栅极层，以及图案化控制栅极层，隔间电介质层和浮栅图案，以形成多个平行与文字线和凹槽区域之间的浮动栅极以及浮动栅极和字线之间的隔间电介质图案，以及露出凹槽区域和字线之间的掩模图案。

6. 发明授权

US07531409B2 Fabrication method and structure for providing a recessed channel in a nonvolatile memory device 有权
标题翻译：用于在非易失性存储器件中提供凹陷通道的制造方法和结构
公开(公告)号：US07531409B2
公开(公告)日：2009-05-12
申请号：US11583796
申请日：2006-10-20
申请人： Sang-Pil Sim , Kwang-soo Kim , Chan-Kwang Park , Heon-Kyu Lee
发明人： Sang-Pil Sim , Kwang-soo Kim , Chan-Kwang Park , Heon-Kyu Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521
摘要： A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.
摘要翻译：制造非易失性存储器件的方法包括制备包括单元阵列区域的半导体衬底。该方法还包括通过蚀刻半导体衬底在电池阵列区域中形成凹陷区域。该方法包括蚀刻半导体衬底的至少一部分，其部分地包括凹陷区域并形成深度不同，与凹陷区域相交并彼此连接的第一和第二沟槽。该方法包括形成具有粗糙底部的器件隔离层，并且通过在第一和第二沟槽中填充绝缘材料来限定有源区。该方法包括在包括凹陷区域的有源区的半导体衬底上形成栅极绝缘层，并在栅极绝缘层上形成栅极结构，以填充凹陷区域，栅极结构包括浮置栅极，栅极间绝缘图案，和控制门。

7. 发明申请

US20090200596A1 FABRICATION METHOD AND STRUCTURE FOR PROVIDING A RECESSED CHANNEL IN A NONVOLATILE MEMORY DEVICE 审中-公开
标题翻译：用于在非易失性存储器件中提供被记录的通道的制造方法和结构
公开(公告)号：US20090200596A1
公开(公告)日：2009-08-13
申请号：US12417127
申请日：2009-04-02
申请人： Sang-Pil Sim , Kwang-soo Kim , Chan-Kwang Park , Heon-Kyu Lee
发明人： Sang-Pil Sim , Kwang-soo Kim , Chan-Kwang Park , Heon-Kyu Lee
IPC分类号： H01L29/788
CPC分类号： H01L27/11524 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L29/40114
摘要： A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.
摘要翻译：制造非易失性存储器件的方法包括制备包括单元阵列区域的半导体衬底。该方法还包括通过蚀刻半导体衬底在电池阵列区域中形成凹陷区域。该方法包括蚀刻半导体衬底的至少一部分，其部分地包括凹陷区域并形成深度不同，与凹陷区域相交并彼此连接的第一和第二沟槽。该方法包括形成具有粗糙底部的器件隔离层，并且通过在第一和第二沟槽中填充绝缘材料来限定有源区。该方法包括在包括凹陷区域的有源区的半导体衬底上形成栅极绝缘层，并在栅极绝缘层上形成栅极结构，以填充凹陷区域，栅极结构包括浮置栅极，栅极间绝缘图案，和控制门。

8. 发明申请

US20070122968A1 Fabrication method and structure for providing a recessed channel in a nonvolatile memory device 有权
标题翻译：用于在非易失性存储器件中提供凹陷通道的制造方法和结构
公开(公告)号：US20070122968A1
公开(公告)日：2007-05-31
申请号：US11583796
申请日：2006-10-20
申请人： Sang-Pil Sim , Kwang-soo Kim , Chan-Kwang Park , Heon-Kyu Lee
发明人： Sang-Pil Sim , Kwang-soo Kim , Chan-Kwang Park , Heon-Kyu Lee
IPC分类号： H01L21/8242 , H01L21/336 , H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521
摘要： A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.
摘要翻译：制造非易失性存储器件的方法包括制备包括单元阵列区域的半导体衬底。该方法还包括通过蚀刻半导体衬底在电池阵列区域中形成凹陷区域。该方法包括蚀刻半导体衬底的至少一部分，其部分地包括凹陷区域并形成深度不同，与凹陷区域相交并彼此连接的第一和第二沟槽。该方法包括形成具有粗糙底部的器件隔离层，并且通过在第一和第二沟槽中填充绝缘材料来限定有源区。该方法包括在包括凹陷区域的有源区的半导体衬底上形成栅极绝缘层，并在栅极绝缘层上形成栅极结构，以填充凹陷区域，栅极结构包括浮置栅极，栅极间绝缘图案，和控制门。

9. 发明授权

US08450170B2 Semiconductor memory device and method of forming the same 有权
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US08450170B2
公开(公告)日：2013-05-28
申请号：US13094229
申请日：2011-04-26
申请人： Ki-Yeol Byun , Chan-Kwang Park , Jae-Hwan Moon , Tae-Wan Lim , Seung-Ah Kim
发明人： Ki-Yeol Byun , Chan-Kwang Park , Jae-Hwan Moon , Tae-Wan Lim , Seung-Ah Kim
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L21/76232 , H01L27/11521
摘要： Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active region. The semiconductor device includes an oxide pattern having a concave top surface between adjacent floating gates. The control gate may be sufficiently spaced apart from the active region by the oxide pattern. The method can provide a semiconductor device that includes a reoxidation process, an active region having a curved edge and an oxide pattern having a top surface of a curved concave shape.
摘要翻译：提供半导体器件和形成半导体器件的方法。半导体器件包括其边缘是弯曲的有源区域。半导体器件包括在有源区上的栅极绝缘层，浮栅，栅极层间介质层和控制栅极线。半导体器件包括在相邻浮动栅极之间具有凹形顶表面的氧化物图案。控制栅极可以通过氧化物图案与有源区足够间隔开。该方法可以提供一种半导体器件，其包括再氧化工艺，具有弯曲边缘的有源区和具有弯曲凹形形状的顶表面的氧化物图案。

10. 发明申请

US20110201189A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US20110201189A1
公开(公告)日：2011-08-18
申请号：US13094229
申请日：2011-04-26
申请人： Ki-Yeol Byun , Chan-Kwang Park , Jae-Hwan Moon , Tae-Wan Lim , Seung-Ah Kim
发明人： Ki-Yeol Byun , Chan-Kwang Park , Jae-Hwan Moon , Tae-Wan Lim , Seung-Ah Kim
IPC分类号： H01L21/28
CPC分类号： H01L27/115 , H01L21/76232 , H01L27/11521
摘要： Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active region. The semiconductor device includes an oxide pattern having a concave top surface between adjacent floating gates. The control gate may be sufficiently spaced apart from the active region by the oxide pattern. The method can provide a semiconductor device that includes a reoxidation process, an active region having a curved edge and an oxide pattern having a top surface of a curved concave shape.
摘要翻译：提供半导体器件和形成半导体器件的方法。半导体器件包括其边缘是弯曲的有源区域。半导体器件包括在有源区上的栅极绝缘层，浮栅，栅极层间介质层和控制栅极线。半导体器件包括在相邻浮动栅极之间具有凹形顶表面的氧化物图案。控制栅极可以通过氧化物图案与有源区足够间隔开。该方法可以提供一种半导体器件，其包括再氧化工艺，具有弯曲边缘的有源区和具有弯曲凹形形状的顶表面的氧化物图案。

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