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    • 2. 发明申请
      US20120146120A1 Non-Volatile Memory Device 审中-公开
    • Non-Volatile Memory Device
    • 非易失性存储器件
    • US20120146120A1
    • 2012-06-14
    • US13236368
    • 2011-09-19
    • Jung-In Han , Sang Eun Lee , Hyouk Sang Yun , Tong-Hyun Shin , June-Ui Song , Hae-Bum Lee , Bong-Yong Lee
    • Jung-In Han , Sang Eun Lee , Hyouk Sang Yun , Tong-Hyun Shin , June-Ui Song , Hae-Bum Lee , Bong-Yong Lee
    • H01L29/78 , H01L27/088
    • H01L27/11521 , H01L27/11519
    • A non-volatile memory device includes memory cell active regions and common source active regions extending in parallel on a semiconductor substrate, a self aligned source active region disposed on the semiconductor substrate that intersects the memory cell active regions and the common source active regions and connects the memory cell active regions to the common source active regions, word lines disposed on the memory cell active regions and the common source active regions that intersect the memory cell active regions and the common source active regions, and memory cell transistors formed by the intersection of the word lines and the memory cell active regions, and common source line transistors formed by the intersection of the word lines and the common source active regions, wherein source and drain regions of each of the common source line transistors are separated from each other in the semiconductor substrate.
    • 非易失性存储器件包括在半导体衬底上平行延伸的存储器单元有源区和共同源极有源区，设置在半导体衬底上的自对准源有源区，与存储单元有源区和公共源有源区相交，并连接 存储单元有效区域到公共源极活性区域，位于存储单元有源区域上的字线和与存储单元有源区域和公共源极有源区域相交的公共源极有源区， 字线和存储单元有源区，以及由字线和公共源有源区的交叉形成的公共源极线晶体管，其中每个公共源极线晶体管的源极和漏极区彼此分离 半导体衬底。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US08897076B2 Non-volatile memory systems having at least one pair of memory cells 有权
    • Non-volatile memory systems having at least one pair of memory cells
    • 具有至少一对存储单元的非易失性存储器系统
    • US08897076B2
    • 2014-11-25
    • US13548506
    • 2012-07-13
    • Bong-Yong Lee , Jung-In Han , Hae-Bum Lee , Sang-Eun Lee , Jung-Ro Ahn , Kyung-Jun Shin , Tae-Hyun Yoon
    • Bong-Yong Lee , Jung-In Han , Hae-Bum Lee , Sang-Eun Lee , Jung-Ro Ahn , Kyung-Jun Shin , Tae-Hyun Yoon
    • G11C16/28 , G11C16/06
    • G11C16/06 , G11C16/28
    • In a non-volatile memory system, a plurality of main memory cells for storing data is arranged in a data cell array and a plurality of reference memory cells is arranged in a reference cell array. The reference cell array includes first reference word lines connected to first reference memory cells and extending, second reference word lines connected to second reference memory cells and extending alternately with the first reference word lines, reference bit lines to which the first and the second reference memory cells are alternately connected in a line and a combined cell having a pair of the first and second reference memory cells and generating a reference signal for processing the data. The first and the second reference memory cells have different cell characteristics. The stability of the reference signal is improved irrespective of the differentiation of the first and the second reference memory cells.
    • 在非易失性存储器系统中，用于存储数据的多个主存储单元被布置在数据单元阵列中，并且多个参考存储单元被布置在参考单元阵列中。 参考单元阵列包括连接到第一参考存储器单元的第一参考字线和连接到第二参考存储器单元并与第一参考字线交替延伸的第二参考字线，第一和第二参考存储器 单元交替地连接在一行中，并且组合单元具有一对第一和第二参考存储单元，并产生用于处理数据的参考信号。 第一和第二参考存储单元具有不同的单元特性。 无论第一和第二参考存储单元的区别如何，参考信号的稳定性得到改善。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US07333367B2 Flash memory devices including multiple dummy cell array regions 有权
    • Flash memory devices including multiple dummy cell array regions
    • 闪存器件包括多个虚拟单元阵列区域
    • US07333367B2
    • 2008-02-19
    • US11602645
    • 2006-11-21
    • Chang-Hyun Lee , Jung-In Han , Kwang-Won Park
    • Chang-Hyun Lee , Jung-In Han , Kwang-Won Park
    • G11C16/06 , G11C16/04
    • G11C7/14 , G11C16/16
    • Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main cell array region are provided. A first erasure voltage is applied to a plurality of main control gate electrodes in the main cell array region. The plurality of main control gate electrodes include a first outermost main control gate electrode adjacent to the first dummy cell array region and a second outermost main control gate electrode adjacent to the second dummy cell array region. A second erasure voltage is applied to an integrated circuit substrate in the main cell array region. The second erasure voltage is greater than the first erasure voltage. A third erasure voltage is applied to a first inner dummy control gate electrode adjacent to the first outermost main control gate electrode and a second inner dummy control gate electrode adjacent to the second outermost main control gate electrode. The third erasure voltage is less than the second erasure voltage. Related devices are also provided.
    • 用于擦除具有包括主单元阵列区域的单元阵列区域，在主单元阵列区域的第一侧上的第一虚设单元阵列区域和第二虚拟单元阵列区域的集成电路存储器件的方法， 提供主单元阵列区域。 第一擦除电压被施加到主单元阵列区域中的多个主控制栅电极。 多个主控制栅极包括与第一虚设单元阵列区域相邻的第一最外侧主控制栅电极和与第二虚设单元阵列区域相邻的第二最外侧主控制栅电极。 第二擦除电压被施加到主单元阵列区域中的集成电路基板。 第二擦除电压大于第一擦除电压。 第三擦除电压被施加到与第一最外面的主控制栅电极相邻的第一内部虚拟控制栅电极和与第二最外面的主控制栅电极相邻的第二内部虚拟控制栅电极。 第三擦除电压小于第二擦除电压。 还提供了相关设备。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 7. 发明申请
      US20070064498A1 Flash memory devices including multiple dummy cell array regions 有权
    • Flash memory devices including multiple dummy cell array regions
    • 闪存器件包括多个虚拟单元阵列区域
    • US20070064498A1
    • 2007-03-22
    • US11602645
    • 2006-11-21
    • Chang-Hyun Lee , Jung-In Han , Kwang-Won Park
    • Chang-Hyun Lee , Jung-In Han , Kwang-Won Park
    • G11C16/04
    • G11C7/14 , G11C16/16
    • Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main cell array region are provided. A first erasure voltage is applied to a plurality of main control gate electrodes in the main cell array region. The plurality of main control gate electrodes include a first outermost main control gate electrode adjacent to the first dummy cell array region and a second outermost main control gate electrode adjacent to the second dummy cell array region. A second erasure voltage is applied to an integrated circuit substrate in the main cell array region. The second erasure voltage is greater than the first erasure voltage. A third erasure voltage is applied to a first inner dummy control gate electrode adjacent to the first outermost main control gate electrode and a second inner dummy control gate electrode adjacent to the second outermost main control gate electrode. The third erasure voltage is less than the second erasure voltage. Related devices are also provided.
    • 用于擦除具有包括主单元阵列区域的单元阵列区域，在主单元阵列区域的第一侧上的第一虚设单元阵列区域和第二虚拟单元阵列区域的集成电路存储器件的方法， 提供主单元阵列区域。 第一擦除电压被施加到主单元阵列区域中的多个主控制栅电极。 多个主控制栅极包括与第一虚设单元阵列区域相邻的第一最外侧主控制栅电极和与第二虚设单元阵列区域相邻的第二最外侧主控制栅电极。 第二擦除电压被施加到主单元阵列区域中的集成电路基板。 第二擦除电压大于第一擦除电压。 第三擦除电压被施加到与第一最外面的主控制栅电极相邻的第一内部虚拟控制栅电极和与第二最外面的主控制栅电极相邻的第二内部虚拟控制栅电极。 第三擦除电压小于第二擦除电压。 还提供了相关设备。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US07158419B2 Methods of fabricating flash memory devices including multiple dummy cell array regions 有权
    • Methods of fabricating flash memory devices including multiple dummy cell array regions
    • 制造包括多个虚拟单元阵列区域的闪速存储器件的方法
    • US07158419B2
    • 2007-01-02
    • US10918966
    • 2004-08-16
    • Chang-Hyun Lee , Jung-In Han , Kwang-Won Park
    • Chang-Hyun Lee , Jung-In Han , Kwang-Won Park
    • G11C16/04 , G11C16/06
    • G11C7/14 , G11C16/16
    • Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main cell array region are provided. A first erasure voltage is applied to a plurality of main control gate electrodes in the main cell array region. The plurality of main control gate electrodes include a first outermost main control gate electrode adjacent to the first dummy cell array region and a second outermost main control gate electrode adjacent to the second dummy cell array region. A second erasure voltage is applied to an integrated circuit substrate in the main cell array region. The second erasure voltage is greater than the first erasure voltage. A third erasure voltage is applied to a first inner dummy control gate electrode adjacent to the first outermost main control gate electrode and a second inner dummy control gate electrode adjacent to the second outermost main control gate electrode. The third erasure voltage is less than the second erasure voltage. Related devices are also provided.
    • 用于擦除具有包括主单元阵列区域的单元阵列区域，在主单元阵列区域的第一侧上的第一虚设单元阵列区域和第二虚拟单元阵列区域的集成电路存储器件的方法， 提供主单元阵列区域。 第一擦除电压被施加到主单元阵列区域中的多个主控制栅电极。 多个主控制栅极包括与第一虚设单元阵列区域相邻的第一最外侧主控制栅电极和与第二虚设单元阵列区域相邻的第二最外侧主控制栅电极。 第二擦除电压被施加到主单元阵列区域中的集成电路基板。 第二擦除电压大于第一擦除电压。 第三擦除电压被施加到与第一最外面的主控制栅电极相邻的第一内部虚拟控制栅电极和与第二最外面的主控制栅电极相邻的第二内部虚拟控制栅电极。 第三擦除电压小于第二擦除电压。 还提供了相关设备。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US07230853B2 Selective erase method for flash memory 失效
    • Selective erase method for flash memory
    • 闪存的选择性擦除方法
    • US07230853B2
    • 2007-06-12
    • US10960542
    • 2004-10-07
    • Wook-Hyun Kwon , Jung-In Han
    • Wook-Hyun Kwon , Jung-In Han
    • G11C16/06
    • G11C16/3445 , G11C16/16 , G11C16/3468 , G11C16/3472 , G11C2216/18
    • Selective erase method for a flash memory device including a group of memory cells arranged in rows and columns include performing an erase operation on the group of memory cells and verifying the erase operation on the group of memory cells to determine threshold voltages of the memory cells. At least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage is identified. A further erase operation is performed on the group of memory cells excluding memory cells of the at least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage.
    • 包括排列成行和列的一组存储器单元的闪速存储器件的选择性擦除方法包括对该组存储器单元执行擦除操作，并验证存储器单元组的擦除操作以确定存储器单元的阈值电压。 识别包括具有低于期望的擦除阈值电压的阈值电压的存储单元的至少一行存储单元。 对包括具有低于期望的擦除阈值电压的阈值电压的存储单元的至少一行存储单元的存储单元排除的存储器单元组执行进一步的擦除操作。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 10. 发明申请
      US20060018163A1 Selective erase method for flash memory 失效
    • Selective erase method for flash memory
    • 闪存的选择性擦除方法
    • US20060018163A1
    • 2006-01-26
    • US10960542
    • 2004-10-07
    • Wook-Hyun Kwon , Jung-In Han
    • Wook-Hyun Kwon , Jung-In Han
    • G11C16/04
    • G11C16/3445 , G11C16/16 , G11C16/3468 , G11C16/3472 , G11C2216/18
    • Selective erase method for a flash memory device including a group of memory cells arranged in rows and columns include performing an erase operation on the group of memory cells and verifying the erase operation on the group of memory cells to determine threshold voltages of the memory cells. At least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage is identified. A further erase operation is performed on the group of memory cells excluding memory cells of the at least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage.
    • 包括排列成行和列的一组存储器单元的闪速存储器件的选择性擦除方法包括对该组存储器单元执行擦除操作，并验证存储器单元组的擦除操作以确定存储器单元的阈值电压。 识别包括具有低于期望的擦除阈值电压的阈值电压的存储单元的至少一行存储单元。 对包括具有低于期望的擦除阈值电压的阈值电压的存储单元的至少一行存储单元的存储单元排除的存储器单元组执行进一步的擦除操作。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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