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1. 发明授权

US08848461B2 Memory cell having flexible read/write assist and method of using 有权
标题翻译：存储单元具有灵活的读/写辅助和使用方法
公开(公告)号：US08848461B2
公开(公告)日：2014-09-30
申请号：US13464489
申请日：2012-05-04
申请人： Jonathan Tsung-Yung Chang , Kun-Hsi Li , Chiting Cheng
发明人： Jonathan Tsung-Yung Chang , Kun-Hsi Li , Chiting Cheng
IPC分类号： G11C7/22
CPC分类号： G11C11/419 , G11C11/41 , G11C29/028 , G11C29/56 , G11C2029/5002 , H01L21/78
摘要： A semiconductor device includes at least one memory cell die. The at least one memory cell die includes a data storage unit. The at least one memory cell die includes at least one read assist enabling unit electrically connected to the data storage unit. The at least one read assist enabling unit configured to lower a voltage of a word line. The memory cell die also includes at least one write assist enabling unit electrically connected to the data storage unit. The at least one write assist enabling unit configured to supply a negative voltage to at least one of a bit line or a bit line bar.
摘要翻译：半导体器件包括至少一个存储单元管芯。至少一个存储单元管芯包括数据存储单元。至少一个存储单元管芯包括电连接到数据存储单元的至少一个读辅助使能单元。所述至少一个读辅助使能单元被配置为降低字线的电压。存储单元管芯还包括电连接到数据存储单元的至少一个写辅助使能单元。所述至少一个写入辅助使能单元被配置为向位线或位线条中的至少一个提供负电压。

2. 发明申请

US20130263066A1 Pre-Colored Methodology of Multiple Patterning 有权
标题翻译：多种图案预色彩方法
公开(公告)号：US20130263066A1
公开(公告)日：2013-10-03
申请号：US13607946
申请日：2012-09-10
申请人： Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
发明人： Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Some embodiments relate to a method of pre-coloring word lines and control lines within an SRAM integrated chip design to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The method is performed by generating a graphical IC layout file having an SRAM circuit with a plurality of word lines and Y-control lines. The word lines and Y-control lines are assigned a color during decomposition. The word lines and Y-control lines are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. Therefore, during mask building, data associated with pre-colored word and Y-control lines is sent to a same mask, regardless of the colors that are assigned to the data. By assigning word and Y-control lines to a same mask through pre-coloring, processing variations between the word and Y-control lines are minimized, thereby mitigating timing variations in an SRAM circuit.
摘要翻译：一些实施例涉及在SRAM集成芯片设计中预先着色字线和控制线的方法，以避免由通过多次图案化光刻工艺引入的处理变化而产生的定时延迟。该方法通过生成具有多个字线和Y控制线的SRAM电路的图形IC布局文件来执行。在分解过程中，字线和Y控制线被分配一个颜色。字线和Y控制线进一步预先着色，以故意将预色数据分配给相同的掩码。因此，在面具构建期间，与预色彩字和Y控制线相关联的数据被发送到相同的掩码，而不管分配给数据的颜色如何。通过预分色将字和Y控制线分配给相同的掩码，字和Y控制线之间的处理变化被最小化，从而减轻SRAM电路中的定时变化。

3. 发明申请

US20130188433A1 MEMORY CIRCUIT AND METHOD OF WRITING DATUM TO MEMORY CIRCUIT 有权
标题翻译：存储器电路和将数据写入存储器电路的方法
公开(公告)号：US20130188433A1
公开(公告)日：2013-07-25
申请号：US13354884
申请日：2012-01-20
申请人： Chih-Yu LIN , Wei Min CHAN , Yen-Huei CHEN , Hung-Jen LIAO , Jonathan Tsung-Yung CHANG
发明人： Chih-Yu LIN , Wei Min CHAN , Yen-Huei CHEN , Hung-Jen LIAO , Jonathan Tsung-Yung CHANG
IPC分类号： G11C7/00
CPC分类号： G11C11/419
摘要： A circuit includes a first node, a second node, a memory cell, a first data line, a second data line, and a write driver. The memory cell is coupled to the first node and the second node and powered by a first voltage at the first node and a second voltage at the second node. The first data line and the second data line are coupled to the memory cell. The write driver has a third node carrying a third voltage less than the first voltage during a write operation. The write deriver is coupled to the first data line and the second data line and configured to, during a write operation, selectively coupling one of the first data line and the second data line to the third node and coupling the other one of the first data line and the second data line to the first node.
摘要翻译：电路包括第一节点，第二节点，存储器单元，第一数据线，第二数据线和写驱动器。存储器单元耦合到第一节点和第二节点，并由第一节点处的第一电压和第二节点处的第二电压供电。第一数据线和第二数据线耦合到存储器单元。写入驱动器具有在写入操作期间承载小于第一电压的第三电压的第三节点。写引导器耦合到第一数据线和第二数据线，并且被配置为在写操作期间，选择性地将第一数据线和第二数据线之一耦合到第三节点，并将第一数据中的另一个耦合线和第二条数据线到第一个节点。

4. 发明申请

US20120307574A1 SRAM READ and WRITE Assist Apparatus 有权
标题翻译： SRAM读写功能
公开(公告)号：US20120307574A1
公开(公告)日：2012-12-06
申请号：US13149611
申请日：2011-05-31
申请人： Chiting Cheng , Chung-Cheng Chou , Jonathan Tsung-Yung Chang
发明人： Chiting Cheng , Chung-Cheng Chou , Jonathan Tsung-Yung Chang
IPC分类号： G11C7/00
CPC分类号： G11C11/419
摘要： A SRAM READ and WRITE assist apparatus comprises a bit line voltage tracking block, a READ assist timer, a READ assist unit, a WRITE assist unit a WRITE control unit. The bit line voltage tracking block detects a voltage on a tracking bit line coupled to a plurality of tracking memory cells. In response to the voltage drop on the tracking bit line, the READ assist timer generates a READ assist pulse. When the READ assist pulse has a logic high state, an activated word line is pulled down to a lower voltage. Such a lower voltage helps to improve the robustness of SRAM memory circuits so as to avoid READ and WRITE failures.
摘要翻译： SRAM读写辅助装置包括位线电压跟踪块，READ辅助定时器，READ辅助单元，WRITE辅助单元，WRITE控制单元。位线电压跟踪块检测耦合到多个跟踪存储器单元的跟踪位线上的电压。响应于跟踪位线上的电压降，READ辅助定时器产生READ辅助脉冲。当READ辅助脉冲具有逻辑高电平状态时，激活的字线被下拉到较低的电压。这样较低的电压有助于提高SRAM存储器电路的鲁棒性，以避免读取和写入故障。

5. 发明申请

US20110161783A1 METHOD AND APPARATUS ON DIRECT MATCHING OF CACHE TAGS CODED WITH ERROR CORRECTING CODES (ECC) 审中-公开
标题翻译：使用错误校正码（ECC）编码的缓存标签的直接匹配的方法和设备
公开(公告)号：US20110161783A1
公开(公告)日：2011-06-30
申请号：US12647932
申请日：2009-12-28
申请人： Dinesh Somasekhar , Jeffrey L. Miller , Gunjan H. Pandya , Tsung-Yung Chang , Wei Wu , Shih-Lien L. Lu
发明人： Dinesh Somasekhar , Jeffrey L. Miller , Gunjan H. Pandya , Tsung-Yung Chang , Wei Wu , Shih-Lien L. Lu
IPC分类号： G06F11/10 , G06F12/06
CPC分类号： G06F11/1064 , G06F12/0895
摘要： An apparatus and method is described herein directly matching coded tags. An incoming tag address is encoded with error correction codes (ECCs) to obtain a coded, incoming tag. The coded, incoming tag is directly compared to a stored, coded tag; this comparison result, in one example, yields an m-bit difference between the coded, incoming tag and the stored, coded tag. ECC, in one described embodiment, is able to correct k-bits and detect k+1 bits. As a result, if the m-bit difference is within 2k+2 bits, then valid codes—coded tags—are detected. As an example, if the m-bit difference is less than a hit threshold, such as k-bits, then a hit is determined, while if the m-bit difference is greater than a miss threshold, such as k+1 bits, then a miss is determined.
摘要翻译：这里描述了直接匹配编码标签的装置和方法。输入标签地址用纠错码（ECC）编码，以获得编码的传入标签。编码的输入标签直接与存储的编码标签进行比较; 在一个示例中，该比较结果在编码的输入标签和存储的编码标签之间产生m位差。在一个所描述的实施例中，ECC能够校正k位并检测k + 1位。结果，如果m位差在2k + 2位之内，则检测有效的代码编码标签。例如，如果m位差小于诸如k位的命中阈值，则确定命中，而如果m位差大于诸如k + 1位的未命中阈值，那么一个小姐是决定的。

6. 发明申请

US20110149666A1 BITLINE FLOATING DURING NON-ACCESS MODE FOR MEMORY ARRAYS 有权
标题翻译：用于存储阵列的非访问模式下的位线浮动
公开(公告)号：US20110149666A1
公开(公告)日：2011-06-23
申请号：US12645623
申请日：2009-12-23
申请人： Tsung-Yung Chang , Fatih Hamzaoglu , Gunjan H. Pandya , Siufu Chiu , Kevin Zhang
发明人： Tsung-Yung Chang , Fatih Hamzaoglu , Gunjan H. Pandya , Siufu Chiu , Kevin Zhang
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C7/12 , G11C5/141 , G11C11/413
摘要： Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.
摘要翻译：公开了允许诸如SRAM的集成电路存储器中的功率节省的技术。这些技术可以体现在允许位线漂移以消除或以其他方式减少与预充电位线相关联的功率泄漏的电路中。例如，这些技术可以体现在具有用于通过唤醒信号对预充电控制信号进行限定的单个逻辑门的位线浮动电路中，从而如果唤醒信号不处于活动状态，则不会发生预充电位线。这些技术还允许消除或减少I / O电路或存储器阵列的不必要的功率消耗，例如当存储器阵列未被访问时或者当阵列或其一部分被永久禁用以用于产量恢复时。

7. 发明授权

US08982659B2 Bitline floating during non-access mode for memory arrays 有权
标题翻译：位线在内存阵列的非访问模式下浮动
公开(公告)号：US08982659B2
公开(公告)日：2015-03-17
申请号：US12645623
申请日：2009-12-23
申请人： Tsung-Yung Chang , Fatih Hamzaoglu , Gunjan H. Pandya , Siufu Chiu , Kevin Zhang , Wei Chen
发明人： Tsung-Yung Chang , Fatih Hamzaoglu , Gunjan H. Pandya , Siufu Chiu , Kevin Zhang , Wei Chen
IPC分类号： G11C5/14 , G11C7/12 , G11C11/413
CPC分类号： G11C7/12 , G11C5/141 , G11C11/413
摘要： Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.
摘要翻译：公开了允许诸如SRAM的集成电路存储器中的功率节省的技术。这些技术可以体现在允许位线漂移以消除或以其他方式减少与预充电位线相关联的功率泄漏的电路中。例如，这些技术可以体现在具有用于通过唤醒信号对预充电控制信号进行限定的单个逻辑门的位线浮动电路中，从而如果唤醒信号不处于活动状态，则不会发生预充电位线。这些技术还允许消除或减少I / O电路或存储器阵列的不必要的功率消耗，例如当存储器阵列未被访问时或者当阵列或其一部分被永久禁用以用于产量恢复时。

8. 发明授权

US08958232B2 Method and apparatus for read assist to compensate for weak bit 有权
标题翻译：用于读取辅助补偿弱点的方法和装置
公开(公告)号：US08958232B2
公开(公告)日：2015-02-17
申请号：US13437081
申请日：2012-04-02
申请人： Jonathan Tsung-Yung Chang , Cheng Hung Lee , Chung-Cheng Chou , Hung-Jen Liao , Bin-Hau Lo
发明人： Jonathan Tsung-Yung Chang , Cheng Hung Lee , Chung-Cheng Chou , Hung-Jen Liao , Bin-Hau Lo
IPC分类号： G11C17/00
CPC分类号： G11C7/12 , G11C7/067 , G11C11/412 , G11C11/419
摘要： A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.
摘要翻译：记忆辅助装置包括检测电路和补偿电路。检测电路被配置为提供一个检测信号，该检测信号指示被配置为对存储在存储位单元中的数据位提供读取访问的位线是否具有低于预定阈值的电压。如果检测信号指示位线的电压低于预定阈值，则补偿电路被配置为下拉位线的电压。

9. 发明授权

US08630132B2 SRAM read and write assist apparatus 有权
标题翻译： SRAM读写辅助装置
公开(公告)号：US08630132B2
公开(公告)日：2014-01-14
申请号：US13149611
申请日：2011-05-31
申请人： Chiting Cheng , Chung-Cheng Chou , Jonathan Tsung-Yung Chang
发明人： Chiting Cheng , Chung-Cheng Chou , Jonathan Tsung-Yung Chang
IPC分类号： G11C7/22
CPC分类号： G11C11/419
摘要： A SRAM READ and WRITE assist apparatus comprises a bit line voltage tracking block, a READ assist timer, a READ assist unit, a WRITE assist unit a WRITE control unit. The bit line voltage tracking block detects a voltage on a tracking bit line coupled to a plurality of tracking memory cells. In response to the voltage drop on the tracking bit line, the READ assist timer generates a READ assist pulse. When the READ assist pulse has a logic high state, an activated word line is pulled down to a lower voltage. Such a lower voltage helps to improve the robustness of SRAM memory circuits so as to avoid READ and WRITE failures.
摘要翻译： SRAM读写辅助装置包括位线电压跟踪块，READ辅助定时器，READ辅助单元，WRITE辅助单元，WRITE控制单元。位线电压跟踪块检测耦合到多个跟踪存储器单元的跟踪位线上的电压。响应于跟踪位线上的电压降，READ辅助定时器产生READ辅助脉冲。当READ辅助脉冲具有逻辑高电平状态时，激活的字线被下拉到较低的电压。这样较低的电压有助于提高SRAM存储器电路的鲁棒性，以避免读取和写入故障。

10. 发明申请

US20130100730A1 METHOD AND APPARATUS FOR WORD LINE SUPPRESSION 有权
标题翻译：方式和装置字线抑制
公开(公告)号：US20130100730A1
公开(公告)日：2013-04-25
申请号：US13279375
申请日：2011-10-24
申请人： Jonathan Tsung-Yung CHANG , Chiting CHENG , Chien-Kuo SU , Chung-Cheng CHOU , Jack LIU
发明人： Jonathan Tsung-Yung CHANG , Chiting CHENG , Chien-Kuo SU , Chung-Cheng CHOU , Jack LIU
IPC分类号： G11C11/40 , G11C5/14 , G11C7/12
CPC分类号： G11C8/08 , G11C11/418
摘要： A memory access operation on a bit cell of a digital memory, e.g., a static random access memory (SRAM), is assisted by reducing the word line control voltage for reading and boosting it for writing, thus improving data integrity. The bit cell has cross coupled inverters for storing and retrieving a logic state via bit line connections through a passing gate transistor controlled by the word line. A level of a word line signal controlling the passing gate transistor is shifted from a first voltage value to a higher second voltage value to begin a memory access cycle. The level of the word line signal is shifted from the second voltage value to a third voltage value less than the second voltage value during the access cycle. The word line signal is maintained at the third voltage value for a time interval during the access cycle.
摘要翻译：数字存储器的位单元（例如静态随机存取存储器（SRAM））上的存储器访问操作通过减少字线控制电压来进行辅助，用于读取和提升其用于写入，从而提高数据完整性。位单元具有交叉耦合的反相器，用于经由位线连接通过由字线控制的通过栅极晶体管来存储和取回逻辑状态。控制通过栅极晶体管的字线信号的电平从第一电压值移位到较高的第二电压值，以开始存储器访问周期。在访问周期期间，字线信号的电平从第二电压值移位到小于第二电压值的第三电压值。在访问周期期间，字线信号保持在第三电压值一段时间间隔。

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