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1. 发明授权

US08958232B2 Method and apparatus for read assist to compensate for weak bit 有权
标题翻译：用于读取辅助补偿弱点的方法和装置
公开(公告)号：US08958232B2
公开(公告)日：2015-02-17
申请号：US13437081
申请日：2012-04-02
申请人： Jonathan Tsung-Yung Chang , Cheng Hung Lee , Chung-Cheng Chou , Hung-Jen Liao , Bin-Hau Lo
发明人： Jonathan Tsung-Yung Chang , Cheng Hung Lee , Chung-Cheng Chou , Hung-Jen Liao , Bin-Hau Lo
IPC分类号： G11C17/00
CPC分类号： G11C7/12 , G11C7/067 , G11C11/412 , G11C11/419
摘要： A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.
摘要翻译：记忆辅助装置包括检测电路和补偿电路。检测电路被配置为提供一个检测信号，该检测信号指示被配置为对存储在存储位单元中的数据位提供读取访问的位线是否具有低于预定阈值的电压。如果检测信号指示位线的电压低于预定阈值，则补偿电路被配置为下拉位线的电压。

2. 发明授权

US08942053B2 Generating and amplifying differential signals 有权
标题翻译：生成和放大差分信号
公开(公告)号：US08942053B2
公开(公告)日：2015-01-27
申请号：US13535075
申请日：2012-06-27
申请人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
发明人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
IPC分类号： G11C7/02 , G11C7/06
CPC分类号： G11C7/067 , G11C7/065
摘要： A circuit includes a first node, a second node, a first current mirror circuit, and a second current mirror circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current mirror circuit is coupled to the first node, and the mirrored end of the first current mirror circuit is coupled to the second node. The second current mirror circuit has a reference end and a mirrored end. The reference end of the second current mirror circuit is coupled to the second node, and the mirrored end of the second current mirror circuit is coupled to the first node.
摘要翻译：电路包括第一节点，第二节点，第一电流镜电路和第二电流镜电路。第一电流镜电路具有参考端和镜像端。第一电流镜电路的参考端耦合到第一节点，并且第一电流镜电路的镜像端耦合到第二节点。第二电流镜电路具有参考端和镜像端。第二电流镜电路的参考端耦合到第二节点，并且第二电流镜电路的镜像端耦合到第一节点。

3. 发明授权

US08355277B2 Biasing circuit and technique for SRAM data retention 有权
标题翻译：用于SRAM数据保留的偏置电路和技术
公开(公告)号：US08355277B2
公开(公告)日：2013-01-15
申请号：US13008992
申请日：2011-01-19
申请人： Hong-Chen Cheng , Chih-Chieh Chiu , Hsu-Shun Chen , Chung-Ji Lu , Cheng Hung Lee , Hung-Jen Liao
发明人： Hong-Chen Cheng , Chih-Chieh Chiu , Hsu-Shun Chen , Chung-Ji Lu , Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C11/413 , G11C5/14
CPC分类号： G11C11/413
摘要： A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.
摘要翻译： SRAM系统包括：耦合在高电源节点和低电源节点之间的SRAM单元阵列，其间限定用于低功率数据保持模式的数据保持电压（VDR）; 主电源开关将高电源和低电源节点之一耦合到主电源，并且在低功率数据保持模式期间将一个高电源和低电源节点与主电源断开; 监控单元，其包括预先装载有数据位的SRAM单元，并且被配置为在SRAM单元阵列中发生数据破坏之前响应于VDR的减小而进行的数据破坏; 以及钳位电源开关，其响应于监视器单元中的数据破坏，将高电源节点和低电源节点中的一个耦合到主电源。

4. 发明授权

US08223571B2 Generating and amplifying differential signals 有权
标题翻译：生成和放大差分信号
公开(公告)号：US08223571B2
公开(公告)日：2012-07-17
申请号：US12839575
申请日：2010-07-20
申请人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
发明人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
IPC分类号： G11C7/02
CPC分类号： G11C7/067 , G11C7/065
摘要： A circuit includes a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.
摘要翻译：电路包括具有第一左漏极，第一左栅极和第一左源的第一左晶体管; 第二左晶体管，具有第二左漏极，第二左栅极和第二左源极; 第三左晶体管，具有第三左漏极，第三左栅极和第三左源; 第一右晶体管，具有第一右漏极，第一右栅极和第一右源; 第二右晶体管，具有第二右漏极，第二右栅极和第二右源; 第三右晶体管，具有第三右漏极，第三右栅极和第三右源; 左节点，电耦合第一左排水口，第二左排水管，第二左闸门，第三右闸门和第三左排水管; 以及电连接第一右排水管，第二右排水管，第二右浇口，第三左浇口和第三右排水沟的右节点。

5. 发明申请

US20100254209A1 Ultra-Low Leakage Memory Architecture 有权
标题翻译：超低泄漏内存架构
公开(公告)号：US20100254209A1
公开(公告)日：2010-10-07
申请号：US12694032
申请日：2010-01-26
申请人： Cheng Hung Lee , Hung-Jen Liao
发明人： Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/063
摘要： An integrated circuit structure includes an active power supply line and a data-retention power supply line. A memory macro is connected to the active power supply line and the data-retention power supply line. The memory macro includes a memory cell array and a switch. The switch is configured to switch a connection between connecting the memory cell array to the active power supply line and connecting the memory cell array to the data-retention power supply line. The data-retention power supply line is outside of the memory macro.
摘要翻译：集成电路结构包括有源电源线和数据保持电源线。存储器宏连接到有源电源线和数据保持电源线。存储器宏包括存储单元阵列和开关。该开关被配置为在将存储单元阵列连接到有源电源线之间切换连接，并将存储单元阵列连接到数据保持电源线。数据保持电源线在存储器宏之外。

6. 发明申请

US20120020176A1 GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS 有权
标题翻译：生成和放大差分信号
公开(公告)号：US20120020176A1
公开(公告)日：2012-01-26
申请号：US12839575
申请日：2010-07-20
申请人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
发明人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
IPC分类号： G11C7/06 , H03F3/45
CPC分类号： G11C7/067 , G11C7/065
摘要： Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.
摘要翻译：一些实施例涉及一种电路，包括：具有第一左漏极，第一左栅极和第一左源的第一左晶体管; 第二左晶体管，具有第二左漏极，第二左栅极和第二左源极; 第三左晶体管，具有第三左漏极，第三左栅极和第三左源; 第一右晶体管，具有第一右漏极，第一右栅极和第一右源; 第二右晶体管，具有第二右漏极，第二右栅极和第二右源; 第三右晶体管，具有第三右漏极，第三右栅极和第三右源; 左节点，电耦合第一左排水口，第二左排水管，第二左闸门，第三右闸门和第三左排水管; 以及电连接第一右排水管，第二右排水管，第二右浇口，第三左浇口和第三右排水沟的右节点。

7. 发明申请

US20080175077A1 Novel write VCCMIN improvement scheme 有权
标题翻译：小写写VCCMIN改进方案
公开(公告)号：US20080175077A1
公开(公告)日：2008-07-24
申请号：US11654983
申请日：2007-01-18
申请人： Cheng Hung Lee , Hung-Jen Liao , Kun-Lung Chen
发明人： Cheng Hung Lee , Hung-Jen Liao , Kun-Lung Chen
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A semiconductor memory is disclosed, which comprises a plurality of memory cells, at least one high voltage power supply (CVDD) line coupled to the plurality of memory cells for supplying power to the same, and at least one controllable discharging circuit coupled between the CVDD line and a complementary low voltage power supply (ground), wherein only during a write operation the controllable discharging circuit is turned on for discharging the CVDD line.
摘要翻译：公开了一种半导体存储器，其包括多个存储器单元，耦合到用于向其供电的多个存储单元的至少一个高压电源（CVDD）线以及耦合在CVDD之间的至少一个可控放电电路线路和互补的低压电源（接地），其中仅在写入操作期间，可控放电电路导通以排出CVDD线。

8. 发明授权

US08792292B2 Providing row redundancy to solve vertical twin bit failures 有权
标题翻译：提供行冗余来解决垂直双位故障
公开(公告)号：US08792292B2
公开(公告)日：2014-07-29
申请号：US13046625
申请日：2011-03-11
申请人： Hong-Chen Cheng , Jung-Ping Yang , Chung-Ji Lu , Derek C. Tao , Cheng Hung Lee , Hung-Jen Liao
发明人： Hong-Chen Cheng , Jung-Ping Yang , Chung-Ji Lu , Derek C. Tao , Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C29/00
CPC分类号： G11C29/846
摘要： A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.
摘要翻译：电路包括被配置为存储第一行地址的故障地址寄存器，耦合到故障地址寄存器的行地址修改器，其中行地址修改器被配置为修改从故障地址寄存器接收的第一行地址以生成第二行地址。第一比较器被配置为接收和比较第一行地址和第三行地址。第二比较器被配置为接收和比较第二行地址和第三行地址。第一行地址和第二行地址是存储器中的失败行地址。

9. 发明授权

US08488395B2 Keepers, integrated circuits, and systems thereof 有权
标题翻译：保管人，集成电路及其系统
公开(公告)号：US08488395B2
公开(公告)日：2013-07-16
申请号：US12754733
申请日：2010-04-06
申请人： Cheng Hung Lee , Ching-Wei Wu , Bin Sheng , Hung-Jen Liao
发明人： Cheng Hung Lee , Ching-Wei Wu , Bin Sheng , Hung-Jen Liao
IPC分类号： G11C7/00
CPC分类号： H01L27/1104 , G11C11/419
摘要： A keeper of an integrated circuit includes a first transistor having a first gate being coupled with an output end of an inverter. A second transistor is coupled with the first transistor in series. The second transistor has a second gate being coupled with an input end of the inverter.
摘要翻译：集成电路的保持器包括具有与反相器的输出端耦合的第一栅极的第一晶体管。第二晶体管与第一晶体管串联耦合。第二晶体管具有与反相器的输入端耦合的第二栅极。

10. 发明申请

US20120230127A1 Providing Row Redundancy to Solve Vertical Twin Bit Failures 有权
标题翻译：提供行冗余来解决垂直双位错误
公开(公告)号：US20120230127A1
公开(公告)日：2012-09-13
申请号：US13046625
申请日：2011-03-11
申请人： Hong-Chen Cheng , Jung-Ping Yang , Chung-Ji Lu , Derek C. Tao , Cheng Hung Lee , Hung-Jen Liao
发明人： Hong-Chen Cheng , Jung-Ping Yang , Chung-Ji Lu , Derek C. Tao , Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C29/04
CPC分类号： G11C29/846
摘要： A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.
摘要翻译：电路包括被配置为存储第一行地址的故障地址寄存器，耦合到故障地址寄存器的行地址修改器，其中行地址修改器被配置为修改从故障地址寄存器接收的第一行地址以生成第二行地址。第一比较器被配置为接收和比较第一行地址和第三行地址。第二比较器被配置为接收和比较第二行地址和第三行地址。第一行地址和第二行地址是存储器中的失败行地址。

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