专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09202541B2 Semiconductor apparatus configured to reduce data processing performance 有权
标题翻译：被配置为降低数据处理性能的半导体装置
公开(公告)号：US09202541B2
公开(公告)日：2015-12-01
申请号：US13607306
申请日：2012-09-07
申请人： Shuuichi Senou , Kenjyu Shimogawa , Susumu Takano , Toshihiko Funaki , Hideaki Arima
发明人： Shuuichi Senou , Kenjyu Shimogawa , Susumu Takano , Toshihiko Funaki , Hideaki Arima
IPC分类号： G06F13/36 , G11C7/22 , G06F13/40 , G06F3/06
CPC分类号： G11C7/22 , G06F3/0635 , G06F13/4022
摘要： A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.
摘要翻译：根据本发明的一个方面的半导体装置包括第一和第二总线接口电路，存储第一和第二模式信息的模式信息存储单元，能够通过第一总线接口设置的第一和第二模式信息电路，基于第一模式信息操作的第一存储器核心，第一存储器核心连接到第一总线接口电路并被提供有第一时钟信号，第二存储器内核，第二存储器核心被提供有第二存储器核心时钟信号和选择电路，其基于预定的切换信息选择性地将第二存储器核心连接到第一或第二总线接口电路，其中当第二存储器核心连接到第二存储器核心时，第二存储器核心基于第二模式信息操作第二总线接口电路。

2. 发明申请

US20130058173A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20130058173A1
公开(公告)日：2013-03-07
申请号：US13607306
申请日：2012-09-07
申请人： Shuuichi SENOU , Kenjyu Shimogawa , Susumu Takano , Toshihiko Funaki , Hideaki Arima
发明人： Shuuichi SENOU , Kenjyu Shimogawa , Susumu Takano , Toshihiko Funaki , Hideaki Arima
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G06F3/0635 , G06F13/4022
摘要： A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.
摘要翻译：根据本发明的一个方面的半导体装置包括第一和第二总线接口电路，存储第一和第二模式信息的模式信息存储单元，能够通过第一总线接口设置的第一和第二模式信息电路，基于第一模式信息操作的第一存储器核心，第一存储器核心连接到第一总线接口电路并被提供有第一时钟信号，第二存储器内核，第二存储器核心被提供有第二存储器核心时钟信号和选择电路，其基于预定的切换信息选择性地将第二存储器核心连接到第一或第二总线接口电路，其中当第二存储器核心连接到第二存储器核心时，第二存储器核心基于第二模式信息操作第二总线接口电路。

3. 发明申请

US20130051110A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20130051110A1
公开(公告)日：2013-02-28
申请号：US13599730
申请日：2012-08-30
申请人： Toshihiko FUNAKI , Toshiharu OKAMOTO , Muneaki MATSUSHIGE , Kenichi KUBOYAMA , Shuuichi SENOU , Susumu TAKANO
发明人： Toshihiko FUNAKI , Toshiharu OKAMOTO , Muneaki MATSUSHIGE , Kenichi KUBOYAMA , Shuuichi SENOU , Susumu TAKANO
IPC分类号： G11C5/06
CPC分类号： G11C7/1048 , G11C7/00 , G11C7/10 , G11C7/1006 , G11C8/12 , G11C11/4096 , H03K5/15006
摘要： A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.
摘要翻译：根据本发明的一个方面的半导体装置包括第一和第二总线接口电路，通过第一数据总线连接到第一总线接口电路的第一存储器核心，第一存储器核心连接到第一存取控制信号从第一总线接口电路输出的第二存储器核心，通过第二数据总线连接到第二总线接口电路的第二存储器核心，以及选择性地将第一存取控制信号和第二存取控制信号输出的第二存取控制信号第二总线接口电路到第二存储器核心。

4. 发明授权

US08760943B2 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US08760943B2
公开(公告)日：2014-06-24
申请号：US13599730
申请日：2012-08-30
申请人： Toshihiko Funaki , Toshiharu Okamoto , Muneaki Matsushige , Kenichi Kuboyama , Shuuichi Senou , Susumu Takano
发明人： Toshihiko Funaki , Toshiharu Okamoto , Muneaki Matsushige , Kenichi Kuboyama , Shuuichi Senou , Susumu Takano
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00 , G11C8/06 , G11C8/12 , G11C11/4096
CPC分类号： G11C7/1048 , G11C7/00 , G11C7/10 , G11C7/1006 , G11C8/12 , G11C11/4096 , H03K5/15006
摘要： A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.
摘要翻译：根据本发明的一个方面的半导体装置包括第一和第二总线接口电路，通过第一数据总线连接到第一总线接口电路的第一存储器核心，第一存储器核心连接到第一存取控制信号从第一总线接口电路输出的第二存储器核心，通过第二数据总线连接到第二总线接口电路的第二存储器核心，以及选择性地将第一存取控制信号和第二存取控制信号输出的第二存取控制信号第二总线接口电路到第二存储器核心。

5. 发明申请

US20120250445A1 SEMICONDUCTOR APPARATUS 审中-公开
公开(公告)号：US20120250445A1
公开(公告)日：2012-10-04
申请号：US13432967
申请日：2012-03-28
申请人： Yasuharu HOSHINO , Toshihiko FUNAKI , Atsunori HIROBE , Tetsuo FUKUSHI
发明人： Yasuharu HOSHINO , Toshihiko FUNAKI , Atsunori HIROBE , Tetsuo FUKUSHI
IPC分类号： G11C8/18 , G11C8/00
CPC分类号： G11C7/10 , G11C7/109 , H03K19/17752
摘要： A semiconductor apparatus includes a programmable logic chip configured to output a control signal, and a memory chip coupled to the programmable logic chip. The memory chip includes a plurality of memory cores, a plurality of bus-interface circuits each configured to couple with the memory cores, and a selection circuit configured to couple the memory cores with one of the bus-interface circuits in response to a predetermined logic level of the control signal.
摘要翻译：半导体装置包括被配置为输出控制信号的可编程逻辑芯片和耦合到可编程逻辑芯片的存储器芯片。存储器芯片包括多个存储器核，多个总线接口电路，每个被配置为与存储器核心耦合;以及选择电路，被配置为响应于预定逻辑将存储器核与总线接口电路之一耦合控制信号的电平。

6. 发明授权

US06937522B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06937522B2
公开(公告)日：2005-08-30
申请号：US10773909
申请日：2004-02-05
申请人： Toshihiko Funaki
发明人： Toshihiko Funaki
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C16/34
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/3454 , G11C2211/5621
摘要： In writing N level of multilevel data to nonvolatile semiconductor memory by repeating a verification process, a verification result of a memory cell where the Nth threshold level which is the highest level is to be written as an expected level is invalidated until completion of writing to a memory cell where the (N−1)th and lower level is to be written. The verification result of the memory cell where the Nth level is to be written is validated after reaching the (N−1)th write level. A reference current supplied to a sense amplifier corresponding to the Nth level is set at at least a level allowing no indeterminate sensing of a sense amplifier. In verification of the Nth level data, a word line voltage supplied for verify-reading is raised from VW 1 to VW 2.
摘要翻译：通过重复验证处理将N级多电平数据写入非易失性半导体存储器，将要写入最高级别的第N阈值水平作为预期级别的存储单元的验证结果无效，直到写入完成为止要写入（N-1）和下一级的存储单元。在达到第（N-1）个写入电平之后验证要写入第N个电平的存储单元的验证结果。提供给对应于第N级的读出放大器的参考电流至少被设置为允许不确定感测读出放大器的电平。在验证第N级数据时，提供用于验证读取的字线电压从V W 1升高到V W 2。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式