专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07719879B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US07719879B2
公开(公告)日：2010-05-18
申请号：US11386811
申请日：2006-03-23
申请人： Muneaki Matsushige , Hiroyuki Satake , Hiroshi Furuta , Toshifumi Takahashi , Hideyuki Nakamura
发明人： Muneaki Matsushige , Hiroyuki Satake , Hiroshi Furuta , Toshifumi Takahashi , Hideyuki Nakamura
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , G11C11/412
摘要： A semiconductor integrated circuit includes a word line extending along a first direction, a first and a second N-well regions, a P-well region disposed between the first and the second N-well regions, a memory cell having a first, second, third, and fourth PMOS transistors, and a first and second NMOS transistors, the first and the second PMOS transistors disposed in the first N-well region along a second direction which is different from the first direction, the first and the second NMOS transistors disposed in the P-well region, and the third and the fourth PMOS transistors disposed in the second N-well region along the second direction.
摘要翻译：半导体集成电路包括沿着第一方向延伸的字线，第一和第二N阱区域，设置在第一和第二N阱区域之间的P阱区域，具有第一，第二，第三和第四PMOS晶体管，以及第一和第二NMOS晶体管，第一和第二PMOS晶体管沿着与第一方向不同的第二方向设置在第一N阱区域中，第一和第二NMOS晶体管被布置以及沿第二方向设置在第二N阱区中的第三和第四PMOS晶体管。

2. 发明授权

US09001591B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09001591B2
公开(公告)日：2015-04-07
申请号：US13479379
申请日：2012-05-24
申请人： Muneaki Matsushige
发明人： Muneaki Matsushige
IPC分类号： G11C11/34 , G11C8/14 , G11C11/4091 , G11C11/4094 , G11C11/4097
CPC分类号： G11C8/14 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： A semiconductor device including multiple subarrays arrayed in a matrix in the row and column directions, and respectively containing multiple memory cells, bit lines coupled to the memory cells, and precharge circuits (to charge the bit lines; column select signal lines extending in the column direction for selecting subarray columns; main word lines for selecting subarray rows; and precharge signal lines for supplying precharge signals to the precharge circuits; and at least two of the subarrays formed in the row direction or the column direction are controlled by the same logic according to the precharge signal.
摘要翻译：一种半导体器件，包括以行和列方向排列成矩阵的多个子阵列，并且分别包含多个存储单元，耦合到存储单元的位线和预充电电路（为位线充电;列列延伸的列选择信号线用于选择子阵列的方向;用于选择子阵列的主字线;以及用于向预充电电路提供预充电信号的预充电信号线;并且在行方向或列方向上形成的至少两个子阵列由相同的逻辑控制，到预充电信号。

3. 发明授权

US08760943B2 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US08760943B2
公开(公告)日：2014-06-24
申请号：US13599730
申请日：2012-08-30
申请人： Toshihiko Funaki , Toshiharu Okamoto , Muneaki Matsushige , Kenichi Kuboyama , Shuuichi Senou , Susumu Takano
发明人： Toshihiko Funaki , Toshiharu Okamoto , Muneaki Matsushige , Kenichi Kuboyama , Shuuichi Senou , Susumu Takano
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00 , G11C8/06 , G11C8/12 , G11C11/4096
CPC分类号： G11C7/1048 , G11C7/00 , G11C7/10 , G11C7/1006 , G11C8/12 , G11C11/4096 , H03K5/15006
摘要： A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.
摘要翻译：根据本发明的一个方面的半导体装置包括第一和第二总线接口电路，通过第一数据总线连接到第一总线接口电路的第一存储器核心，第一存储器核心连接到第一存取控制信号从第一总线接口电路输出的第二存储器核心，通过第二数据总线连接到第二总线接口电路的第二存储器核心，以及选择性地将第一存取控制信号和第二存取控制信号输出的第二存取控制信号第二总线接口电路到第二存储器核心。

4. 发明授权

US08335116B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08335116B2
公开(公告)日：2012-12-18
申请号：US13014510
申请日：2011-01-26
申请人： Muneaki Matsushige , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
发明人： Muneaki Matsushige , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
IPC分类号： G11C7/00 , G11C8/00 , G11C8/16
CPC分类号： G11C7/00 , G11C7/10
摘要： A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.
摘要翻译：半导体存储装置包括：多个存储单元阵列; 多个双向数据总线，与所述多个存储单元阵列中的相应数据总线相对应地设置; 多个双向缓冲电路，其与存储单元阵列相对应地设置，能够连续地连接相邻的双向数据总线，以便中继双向数据总线中的数据; 以及用于控制双向缓冲电路的激活的控制电路。双向缓冲电路被布置为反转逻辑，并且双向缓冲电路被布置成不反转逻辑。

5. 发明申请

US20120241860A1 SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING TRANSISTOR HAVING DIFFUSION LAYER FORMED AT OUTSIDE OF ELEMENT ISOLATION REGION FOR PREVENTING SOFT ERROR 失效
标题翻译：半导体集成电路，包括在元件隔离区域形成的扩散层的晶体管，用于防止软错误
公开(公告)号：US20120241860A1
公开(公告)日：2012-09-27
申请号：US13437311
申请日：2012-04-02
申请人： Hiroshi Furuta , Shouzou Uchida , Muneaki Matsushige , Junji Monden
发明人： Hiroshi Furuta , Shouzou Uchida , Muneaki Matsushige , Junji Monden
IPC分类号： H01L27/092
CPC分类号： H01L27/0207 , H01L27/0921 , H01L29/0653
摘要： A semiconductor integrated circuit device includes a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET, a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of a plurality of ones of the MISFET provided in two regions with a drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode, and a second diffusion layer having a conductivity type different from that of the drain diffusion layer of the one of the plurality of ones of the MISFET provided between the well isolation boundary phase and one of a source diffusion layer and the drain diffusion layer.
摘要翻译：半导体集成电路器件包括：P沟道MISFET（金属 - 绝缘体 - 半导体场效应晶体管）和N沟道MISFET中的至少一个的栅极电极，其设置在与阱隔离边界相位方向平行的方向上在所述P沟道MISFET和所述N沟道MISFET之间的第一扩散层具有与设置在两个区域中的多个MISFET中的一个的漏极扩散层相同的导电类型的第一扩散层， MISFET，其分别在与栅电极正交的方向上分离，第二扩散层的导电类型与漏极扩散层的漏极扩散层的导电类型不同，所述漏极扩散层设置在阱隔离边界相之间以及源极扩散层和漏极扩散层中的一个。

6. 发明申请

US20080099857A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20080099857A1
公开(公告)日：2008-05-01
申请号：US11907327
申请日：2007-10-11
申请人： Hiroshi Furuta , Junji Monden , Shouzou Uchida , Muneaki Matsushige
发明人： Hiroshi Furuta , Junji Monden , Shouzou Uchida , Muneaki Matsushige
IPC分类号： H01L29/94
CPC分类号： H01L29/4238 , H01L21/823425 , H01L21/823481 , H01L27/0705
摘要： A semiconductor integrated circuit device includes a first and a second field-effect transistors having a gate electrode formed as a ring shape, a drain diffusion layer formed inside the gate electrode and a source diffusion layer formed outside the gate electrode and a substrate potential diffusion layer or a well potential diffusion layer disposed to contact each of the source diffusion layers of the first and the second field-effect transistors of the same conductivity type, the substrate potential diffusion layer or the well potential diffusion layer being formed with a semiconductor of a different conductivity type from the source diffusion layer. Different signals are input to each of the gate electrodes, the substrate potential diffusion layer or the well potential diffusion layer are formed between the source diffusion layer of the first field-effect transistor and the source diffusion layer of the second field-effect transistor.
摘要翻译：半导体集成电路器件包括具有形成为环状的栅电极的第一和第二场效应晶体管，形成在栅电极内部的漏极扩散层和形成在栅电极外部的源极扩散层和衬底电位扩散层或设置成与相同导电类型的第一和第二场效应晶体管的每个源极扩散层接触的阱势扩散层，衬底电位扩散层或阱电位扩散层由不同的半导体形成源极扩散层的导电类型。对每个栅电极输入不同的信号，在第一场效应晶体管的源极扩散层和第二场效应晶体管的源极扩散层之间形成衬底电位扩散层或阱电位扩散层。

7. 发明申请

US20070208982A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070208982A1
公开(公告)日：2007-09-06
申请号：US11583728
申请日：2006-10-20
申请人： Muneaki Matsushige , Hiroyuki Satake
发明人： Muneaki Matsushige , Hiroyuki Satake
IPC分类号： G01R31/28
CPC分类号： G11C5/005 , G11C11/4125 , H03K5/15093
摘要： A semiconductor integrated circuit apparatus of the present invention includes a periodical signal generation circuit connected with N logical circuits, wherein the N is a natural number, outputting a periodical signal. The periodic signal generation circuit includes a reset circuit outputting a reset signal initializing according to outputs from a first stage logic circuit to N-1th logic circuit.
摘要翻译：本发明的半导体集成电路装置包括与N个逻辑电路连接的周期信号生成电路，其中N是自然数，输出周期信号。周期信号发生电路包括复位电路，其根据从第一级逻辑电路到第N-1逻辑电路的输出输出复位信号初始化。

8. 发明授权

US07808056B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07808056B2
公开(公告)日：2010-10-05
申请号：US11907327
申请日：2007-10-11
申请人： Hiroshi Furuta , Junji Monden , Shouzou Uchida , Muneaki Matsushige
发明人： Hiroshi Furuta , Junji Monden , Shouzou Uchida , Muneaki Matsushige
IPC分类号： H01L27/088
CPC分类号： H01L29/4238 , H01L21/823425 , H01L21/823481 , H01L27/0705
摘要： A semiconductor integrated circuit device includes a first field-effect transistor and a second field-effect transistor, each of the first field-effect transistor and the second field-effect transistor having a gate electrode formed as a ring shape, a drain diffusion layer formed inside the gate electrode and a source diffusion layer formed outside the gate electrode and a substrate potential diffusion layer or a well potential diffusion layer disposed to contact each of the source diffusion layers of the first and the second field-effect transistors of the same conductivity type, the substrate potential diffusion layer or the well potential diffusion layer being formed with a semiconductor of a different conductivity type from the source diffusion layer. Different signals are input to each of the gate electrodes, the substrate potential diffusion layer or the well potential diffusion layer are formed between the source diffusion layer of the first field-effect transistor and the source diffusion layer of the second field-effect transistor.
摘要翻译：半导体集成电路器件包括第一场效应晶体管和第二场效应晶体管，第一场效应晶体管和第二场效应晶体管中的每一个具有形成为环形的栅电极，形成漏极扩散层在栅极电极内部形成源极扩散层，以及形成在栅电极外部的源极扩散层和与第一和第二场效应晶体管的相同导电类型的每个源极扩散层接触的衬底电位扩散层或阱电位扩散层基板电位扩散层或阱电位扩散层由与源极扩散层不同的导电类型的半导体形成。对每个栅电极输入不同的信号，在第一场效应晶体管的源极扩散层和第二场效应晶体管的源极扩散层之间形成衬底电位扩散层或阱电位扩散层。

9. 发明申请

US20060215441A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US20060215441A1
公开(公告)日：2006-09-28
申请号：US11386811
申请日：2006-03-23
申请人： Muneaki Matsushige , Hiroyuki Satake , Hiroshi Furuta , Toshifumi Takahashi , Hideyuki Nakamura
发明人： Muneaki Matsushige , Hiroyuki Satake , Hiroshi Furuta , Toshifumi Takahashi , Hideyuki Nakamura
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , G11C11/412
摘要： A semiconductor integrated circuit includes a word line extending along a first direction, a first and a second N-well regions, a P-well region disposed between the first and the second N-well regions, a memory cell having a first, second, third, and fourth PMOS transistors, and a first and second NMOS transistors, the first and the second PMOS transistors disposed in the first N-well region along a second direction which is different from the first direction, the first and the second NMOS transistors disposed in the P-well region, and the third and the fourth PMOS transistors disposed in the second N-well region along the second direction.
摘要翻译：半导体集成电路包括沿着第一方向延伸的字线，第一和第二N阱区域，设置在第一和第二N阱区域之间的P阱区域，具有第一，第二，第三和第四PMOS晶体管，以及第一和第二NMOS晶体管，第一和第二PMOS晶体管沿着与第一方向不同的第二方向设置在第一N阱区域中，第一和第二NMOS晶体管被布置以及沿第二方向设置在第二N阱区中的第三和第四PMOS晶体管。

10. 发明授权

US08471336B2 Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error 失效
标题翻译：包括晶体管的半导体集成电路，其具有形成在元件隔离区域外部的扩散层，以防止软错误
公开(公告)号：US08471336B2
公开(公告)日：2013-06-25
申请号：US13437311
申请日：2012-04-02
申请人： Hiroshi Furuta , Shouzou Uchida , Muneaki Matsushige , Junji Monden
发明人： Hiroshi Furuta , Shouzou Uchida , Muneaki Matsushige , Junji Monden
IPC分类号： H01L29/76
CPC分类号： H01L27/0207 , H01L27/0921 , H01L29/0653
摘要： A semiconductor integrated circuit device includes a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET, a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of a plurality of ones of the MISFET provided in two regions with a drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode, and a second diffusion layer having a conductivity type different from that of the drain diffusion layer of the one of the plurality of ones of the MISFET provided between the well isolation boundary phase and one of a source diffusion layer and the drain diffusion layer.
摘要翻译：半导体集成电路器件包括：P沟道MISFET（金属 - 绝缘体 - 半导体场效应晶体管）和N沟道MISFET中的至少一个的栅极电极，其设置在与阱隔离边界相位方向平行的方向上在所述P沟道MISFET和所述N沟道MISFET之间的第一扩散层具有与设置在两个区域中的多个MISFET中的一个的漏极扩散层相同的导电类型的第一扩散层， MISFET，其分别在与栅电极正交的方向上分离，第二扩散层的导电类型与漏极扩散层的漏极扩散层的导电类型不同，所述漏极扩散层设置在阱隔离边界相之间以及源极扩散层和漏极扩散层中的一个。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式