专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5463584A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5463584A
公开(公告)日：1995-10-31
申请号：US243009
申请日：1994-05-16
申请人： Yasuharu Hoshino
发明人： Yasuharu Hoshino
IPC分类号： G11C7/10 , G11C11/4096 , G11C7/00 , G11C8/00
CPC分类号： G11C7/106 , G11C11/4096 , G11C7/1006 , G11C7/1051
摘要： The semiconductor memory device according to the present invention includes a plurality of memory cells that are provided in array form and a plurality of bit lines and word lines that are respectively connected to these memory cells, and comprises a memory cell array arranged so as to form pairs of bit lines, a data register circuit consisting of a plurality of registers, and selection means for respectively connecting predetermined bit line pairs out of the plurality of bit line pairs to a plurality of registers in response to a control signal.This data register circuit is formed by arranging the plurality of registers in a single line.With such a constitution, the number of registers that constitute the data register circuit can be reduced compared with the conventional device. Accordingly, it becomes possible to arrange the registers in a single line, the area for the data register circuit can sharply be reduced in comparison to the case of the conventional device, contributing to the integration of the semiconductor memory device.
摘要翻译：根据本发明的半导体存储器件包括以阵列形式提供的多个存储器单元和分别连接到这些存储单元的多个位线和字线，并且包括布置成形成的存储单元阵列位线对，由多个寄存器组成的数据寄存器电路以及用于响应于控制信号将多个位线对中的预定位线对分别连接到多个寄存器的选择装置。该数据寄存器电路通过将多个寄存器布置在一条线中而形成。通过这样的结构，与传统的装置相比，可以减少构成数据寄存器电路的寄存器的数量。因此，与现有技术的装置相比，可以将寄存器配置在一条直线上，数据寄存器电路的面积可以大大降低，有助于半导体存储器件的集成。

2. 发明申请

US20120250445A1 SEMICONDUCTOR APPARATUS 审中-公开
公开(公告)号：US20120250445A1
公开(公告)日：2012-10-04
申请号：US13432967
申请日：2012-03-28
申请人： Yasuharu HOSHINO , Toshihiko FUNAKI , Atsunori HIROBE , Tetsuo FUKUSHI
发明人： Yasuharu HOSHINO , Toshihiko FUNAKI , Atsunori HIROBE , Tetsuo FUKUSHI
IPC分类号： G11C8/18 , G11C8/00
CPC分类号： G11C7/10 , G11C7/109 , H03K19/17752
摘要： A semiconductor apparatus includes a programmable logic chip configured to output a control signal, and a memory chip coupled to the programmable logic chip. The memory chip includes a plurality of memory cores, a plurality of bus-interface circuits each configured to couple with the memory cores, and a selection circuit configured to couple the memory cores with one of the bus-interface circuits in response to a predetermined logic level of the control signal.
摘要翻译：半导体装置包括被配置为输出控制信号的可编程逻辑芯片和耦合到可编程逻辑芯片的存储器芯片。存储器芯片包括多个存储器核，多个总线接口电路，每个被配置为与存储器核心耦合;以及选择电路，被配置为响应于预定逻辑将存储器核与总线接口电路之一耦合控制信号的电平。

3. 发明授权

US5631713A Video processor with field memory for exclusively storing picture information 失效
标题翻译：具有专用存储图像信息的场存储器的视频处理器
公开(公告)号：US5631713A
公开(公告)日：1997-05-20
申请号：US392179
申请日：1995-02-22
申请人： Yasuharu Hoshino
发明人： Yasuharu Hoshino
IPC分类号： H04N5/907 , H04N5/937 , H04N9/87 , H04N5/14
CPC分类号： H04N5/4448 , H04N5/45 , H04N5/907
摘要： In a Video processor, an analog composite video signal is converted by an A/D converter (10) to a digital bit sequence in response to a system clock pulse. By using the system clock pulse and horizontal and vertical synchronizing pulses separated from the composite signal, a horizontal blanking interval and a vertical blanking interval are detected by control circuitry (21.about.24) and the read/write operations of a field memory (12) are disabled during the horizontal and vertical blanking intervals and enabled at other times. The picture information from the memory is converted by a D/A converter (13) to analog form in response to the system clock pulse. A multiplex of a digital pedestal level signal and a digital synchronization level signal is supplied to the D/A converter (13) when the memory is disabled.
摘要翻译：在视频处理器中，响应于系统时钟脉冲，模拟复合视频信号由A / D转换器（10）转换成数字位序列。通过使用从复合信号分离的系统时钟脉冲和水平和垂直同步脉冲，控制电路（21差分24）和场存储器（12）的读/写操作检测水平消隐间隔和垂直消隐间隔，在水平和垂直消隐间隔期间禁用，并在其他时间启用。响应于系统时钟脉冲，来自存储器的图像信息被D / A转换器（13）转换为模拟形式。当禁止存储器时，数字基准电平信号和数字同步电平信号的多路复用被提供给D / A转换器（13）。

4. 发明授权

US5343439A Memory apparatus 失效
标题翻译：存储设备
公开(公告)号：US5343439A
公开(公告)日：1994-08-30
申请号：US779087
申请日：1991-10-18
申请人： Yasuharu Hoshino
发明人： Yasuharu Hoshino
IPC分类号： G11C7/00 , G11C7/10 , G11C11/401 , G11C29/00 , G11C29/04
CPC分类号： G11C7/1072
摘要： A memory apparatus includes a memory cell array for storing a data, a shift register for receiving an input serial data to be stored in the memory cell array and supplying an output serial data to be read from the memory cell array, and a transfer gate for transferring a data in parallel between the shift register and the memory cell array. In the shift register, the input serial data is shifted to an output side thereof until the first bit reaches to the final step thereof. Then, the input serial data is transferred to be stored in the memory cell array by the transfer gate. Thus, when the stored data is read therefrom, no invalid bit is supplied even at the beginning time even if the shift register is longer than the input serial data.
摘要翻译：存储装置包括用于存储数据的存储单元阵列，用于接收要存储在存储单元阵列中的输入串行数据并提供要从存储单元阵列读取的输出串行数据的移位寄存器，以及用于在移位寄存器和存储单元阵列之间并行传送数据。在移位寄存器中，输入串行数据被移位到其输出侧，直到第一位到达其最后一步。然后，输入串行数据被传送到存储单元阵列中，由传输门。因此，当存储的数据被读出时，即使在移位寄存器比输入的串行数据长的情况下，即使在开始时也不提供无效的位。

5. 发明授权

US5187684A Semiconductor memory device with read/write controlling unit for concurrently writing a data bit into memory cells 失效
标题翻译：具有用于将数据位同时写入存储单元的读/写控制单元的半导体存储器件
公开(公告)号：US5187684A
公开(公告)日：1993-02-16
申请号：US673317
申请日：1991-03-22
申请人： Yasuharu Hoshino
发明人： Yasuharu Hoshino
IPC分类号： G11C11/401 , G11C8/10
CPC分类号： G11C8/10
摘要： A semiconductor memory device comprises a plurality of memory cells respectively storing data bits in a rewritable manner, a plurality of digit lines coupled to the memory cells, a column selector unit having a plurality of transfer gate transistors coupled between the digit lines and a data line, and a read/write controlling unit responsive to address bits and allowing one of the transfer gate transistors to couple the data line to the associated digit line, wherein the read/write controlling unit is further responsive to a bit pattern stored in a register and allows a plurality of transfer gate transistors to couple the data line to the associated digit lines so that a new data bit is concurrently written into a plurality of memory cells.
摘要翻译：半导体存储器件包括分别以可重写方式存储数据位的多个存储器单元，耦合到存储单元的多个数字线，列选择器单元，其具有耦合在数字线和数据线之间的多个传输栅极晶体管以及读/写控制单元，其响应于地址位并且允许传输门晶体管中的一个将数据线耦合到相关联的数字线，其中读/写控制单元还响应于存储在寄存器中的位模式，允许多个传输栅极晶体管将数据线耦合到相关联的数字线，使得新的数据位同时写入多个存储单元。

6. 发明授权

US5317539A Dynamic random access memory for video 失效
标题翻译：视频的动态随机存取存储器
公开(公告)号：US5317539A
公开(公告)日：1994-05-31
申请号：US905418
申请日：1992-06-29
申请人： Yasuharu Hoshino
发明人： Yasuharu Hoshino
IPC分类号： G11C11/409 , G11C7/00 , G11C11/401 , G11C11/407 , G06F12/00
CPC分类号： G11C7/00
摘要： A semiconductor memory includes a memory cell array having a plurality of memory cells, a plurality of bit line pairs and word lines, a sense amplifier connected to each member of the bit line pair, a transfer gate provided between one end of the bit line and the sense amplifier, and a potential supply circuit connected respectively to the bit line pairs between the sense amplifiers.
摘要翻译：半导体存储器包括具有多个存储单元的存储单元阵列，多个位线对和字线，连接到位线对的每个构件的读出放大器，位于位线的一端和读出放大器和分别连接在读出放大器之间的位线对的电位电路。

7. 发明授权

US5144584A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5144584A
公开(公告)日：1992-09-01
申请号：US622067
申请日：1990-12-04
申请人： Yasuharu Hoshino
发明人： Yasuharu Hoshino
IPC分类号： G11C11/401 , G11C11/406
CPC分类号： G11C11/406
摘要： A semiconductor memory device comprises a random memory cell array halved into first and second memory areas, and a data register coupled to digit lines of the random memory cell array in parallel for temporarily holding data read out onto the respective digit lines from selected memory cells. A row address generator receives an input row address and generates a first row address signal designating a first row corresponding to the input row address, and a second row address designating a second row different from the first row. A controller is coupled to first and second half portions of each of the word lines, and responds to the first and second row address signals so as to cause to transfer to the data register, data stored in the memory cells which are included in one row designated by the first row address signal and which belong to one of the first and second memory areas, and also so as to cause to refresh the memory cells which are included in one row designated by the second row address signal and which belong to the other of the first and second memory areas.
摘要翻译：一个半导体存储器件包括一个被分成第一和第二存储器区域的随机存储器单元阵列，以及一个与随机存储单元阵列的数字线并联耦合的数据寄存器，用于临时保存从所选择的存储器单元读出到各个数字线上的数据。行地址生成器接收输入行地址，并生成指定对应于输入行地址的第一行的第一行地址信号和指定与第一行不同的第二行的第二行地址。控制器耦合到每个字线的第一和第二半部分，并且响应于第一和第二行地址信号，从而将存储在包括在一行中的存储单元中的数据传送到数据寄存器由第一行地址信号指定并且属于第一和第二存储区域中的一个，并且还使得刷新由第二行地址信号指定并属于另一行地址信号的一行中包括的存储单元的第一和第二记忆区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式