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    • 4. 发明授权
    • Compound type heat exchanger
    • 复合式换热器
    • US07077193B2
    • 2006-07-18
    • US10842118
    • 2004-05-10
    • Naohisa KamiyamaToshiharu Watanabe
    • Naohisa KamiyamaToshiharu Watanabe
    • F28F9/02
    • F28F1/126F28D1/0443F28F13/00F28F2009/0287F28F2270/00
    • A compound type heat exchanger has an oil cooler unit and a condenser unit integrated with each other. Both of the units have a plurality of heat exchanging pipes and fins juxtaposed and alternately stacked into a lamination, in common. At both ends of the lamination in the longitudinal direction of the pipes, they are connected with header pipes. At a boundary between the units, the heat exchanger includes partition walls arranged in the header pipes and a pseudo heat exchanging passage member interposed in the lamination. Further, at least either one of two fins adjoining the pseudo heat exchanging passage member on the side of the oil cooler unit and also on the side of the condenser unit is joined to the pseudo heat exchanging passage member, while the other fins are joined to the pipes.
    • 复合式热交换器具有油冷却器单元和彼此结合的冷凝器单元。 这两个单元共同地具有多个热交换管和翅片并置并交替堆叠成层叠。 在管道的纵向层叠的两端,它们与总管连接。 在单元之间的边界处,热交换器包括布置在集管中的分隔壁和插入层叠中的假热交换通道构件。 此外,在油冷却器单元一侧以及冷凝器单元一侧与假热交换通道构件相邻的两个翅片中的至少任一个接合到假热交换通道构件,而另一个翅片连接到 管道。
    • 8. 发明授权
    • Nonvolatile semiconductor memory having control gate with top flat surface covering storage layers of two adjacent transistors
    • 具有控制栅极的非易失性半导体存储器,其顶部平坦表面覆盖两个相邻晶体管的存储层
    • US06762955B2
    • 2004-07-13
    • US10422900
    • 2003-04-25
    • Koji SakuiToshiharu Watanabe
    • Koji SakuiToshiharu Watanabe
    • G11C1604
    • H01L27/11521G11C16/0483H01L27/115H01L27/11524
    • A nonvolatile semiconductor memory includes rewritable nonvolatile memory cell transistors connected in series. The nonvolatile memory cell transistors includes at least two charge storage layers formed on a first insulating film, a control gate shared by two adjacent transistors which are two of the nonvolatile memory cell transistors and which are adjacent to each other, and a second insulating film formed between the at least two charge storage layers and the control gate. A top of the control gate has a flat surface that covers the at least two charge storage layers that correspond to the two adjacent transistors, and the flat surface extends from one of the at least two charge storage layers to the other of the at least two charge storage layers.
    • 非易失性半导体存储器包括串联连接的可重写非易失性存储单元晶体管。 非易失性存储单元晶体管包括形成在第一绝缘膜上的至少两个电荷存储层,由两个非易失性存储单元晶体管彼此相邻并且彼此相邻的两个相邻晶体管共享的控制栅极和形成的第二绝缘膜 在所述至少两个电荷存储层和所述控制栅极之间。 控制栅极的顶部具有覆盖对应于两个相邻晶体管的至少两个电荷存储层的平坦表面,并且平坦表面从至少两个电荷存储层中的一个延伸到至少两个电荷存储层中的另一个 电荷存储层。
    • 10. 发明授权
    • Semiconductor device having MISFETs
    • 具有MISFET的半导体器件
    • US06376879B2
    • 2002-04-23
    • US09327517
    • 1999-06-08
    • Seiichi MoriToshiharu WatanabeMasataka TakebuchiKazuaki Isobe
    • Seiichi MoriToshiharu WatanabeMasataka TakebuchiKazuaki Isobe
    • H01L2978
    • H01L21/76897H01L21/823425H01L27/10873H01L27/10894
    • A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor. The LDD of the low voltage transistor is provided in that part of the substrate which lies right below the first side-wall film. The drain/source diffusion layer of the low voltage transistor is provided in two continuous parts of the substrate which lie, respectively, right below and outside the second side-wall film.
    • 第一侧壁膜形成在高电压晶体管的栅电极的侧面上,第二侧壁膜设置在第一侧壁膜上。 第一侧壁膜的蚀刻速率低于预金属电介质的蚀刻速率,并且第二侧壁膜的蚀刻速率基本上等于前金属电介质的蚀刻速率。 高压晶体管的LDD设置在半导体衬底的位于第一和第二侧壁膜正下方的部分中。 高压晶体管的源极/漏极扩散层形成在第二侧壁膜外侧的基板的那部分。 蚀刻速度低于预金属电介质的蚀刻速率的第一侧壁膜和/或具有与前金属电介质基本上相同的蚀刻速率的第二侧壁膜设置在栅极的侧面 低压晶体管的电极。 低压晶体管的LDD设置在基板的位于第一侧壁膜正下方的部分。 低压晶体管的漏极/源极扩散层设置在分别位于第二侧壁膜的正下方和外侧的基板的两个连续部分中。