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1. 发明授权

US06762955B2 Nonvolatile semiconductor memory having control gate with top flat surface covering storage layers of two adjacent transistors 失效
标题翻译：具有控制栅极的非易失性半导体存储器，其顶部平坦表面覆盖两个相邻晶体管的存储层
公开(公告)号：US06762955B2
公开(公告)日：2004-07-13
申请号：US10422900
申请日：2003-04-25
申请人： Koji Sakui , Toshiharu Watanabe
发明人： Koji Sakui , Toshiharu Watanabe
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes rewritable nonvolatile memory cell transistors connected in series. The nonvolatile memory cell transistors includes at least two charge storage layers formed on a first insulating film, a control gate shared by two adjacent transistors which are two of the nonvolatile memory cell transistors and which are adjacent to each other, and a second insulating film formed between the at least two charge storage layers and the control gate. A top of the control gate has a flat surface that covers the at least two charge storage layers that correspond to the two adjacent transistors, and the flat surface extends from one of the at least two charge storage layers to the other of the at least two charge storage layers.
摘要翻译：非易失性半导体存储器包括串联连接的可重写非易失性存储单元晶体管。非易失性存储单元晶体管包括形成在第一绝缘膜上的至少两个电荷存储层，由两个非易失性存储单元晶体管彼此相邻并且彼此相邻的两个相邻晶体管共享的控制栅极和形成的第二绝缘膜在所述至少两个电荷存储层和所述控制栅极之间。控制栅极的顶部具有覆盖对应于两个相邻晶体管的至少两个电荷存储层的平坦表面，并且平坦表面从至少两个电荷存储层中的一个延伸到至少两个电荷存储层中的另一个电荷存储层。

2. 发明授权

US06577533B2 Nonvolatile semiconductor memory and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US06577533B2
公开(公告)日：2003-06-10
申请号：US09814711
申请日：2001-03-23
申请人： Koji Sakui , Toshiharu Watanabe
发明人： Koji Sakui , Toshiharu Watanabe
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524
摘要： A trench region is formed in a memory cell P-type well. Two NAND-type memory cell units are respectively formed along both side wall portions of this trench region. A floating gate and a control gate in these NAND-type memory cell units are formed self-aligningly without using a photoresist. One bit line connected to the two NAND-type memory cell units is formed via an interlayer dielectric. The bit line pitch of this bit line is set at 2 F. Hence, the size of a nonvolatile semiconductor memory can be reduced.
摘要翻译：在存储单元P型阱中形成沟槽区域。沿着该沟槽区域的两个侧壁部分分别形成两个NAND型存储单元。这些NAND型存储单元单元中的浮置栅极和控制栅极自动对准地形成，而不使用光致抗蚀剂。通过层间电介质形成连接到两个NAND型存储单元单元的一位线。该位线的位线间距设置为2μF。因此，可以减小非易失性半导体存储器的尺寸。

3. 发明授权

US07115474B2 Nonvolatile semiconductor memory and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07115474B2
公开(公告)日：2006-10-03
申请号：US10866137
申请日：2004-06-14
申请人： Koji Sakui , Toshiharu Watanabe
发明人： Koji Sakui , Toshiharu Watanabe
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524
摘要： A trench region 14 is formed in a memory cell P-type well 13. Two NAND-type memory cell units ND1 and ND2 are respectively formed along both side wall portions of this trench region 14. A floating gate FG and a control gate CG in these NAND-type memory cell units ND1 and ND2 are formed self-aligningly without using memory cell units ND1 and ND2 is formed via an interlayer dielectric 30. The bit line pitch of this bit line BL is set at 2 F. Hence, the size of a nonvolatile semiconductor memory can be reduced.
摘要翻译：沟槽区14形成在存储单元P型阱13中。两个NAND型存储单元ND 1和ND 2分别沿着该沟槽区域14的两个侧壁部分形成。这些NAND型存储单元单元ND 1和ND 2中的浮栅FG和控制栅极CG形成在不使用存储单元单元ND 1和ND 2的情况下，通过层间电介质30形成自对准。该位线BL的位线间距设定为2μF。因此，可以减小非易失性半导体存储器的尺寸。

4. 发明授权

US08737131B2 Programming memory cells using smaller step voltages for higher program levels 有权
标题翻译：使用更小的步进电压编程存储器单元以实现更高的程序级
公开(公告)号：US08737131B2
公开(公告)日：2014-05-27
申请号：US13305795
申请日：2011-11-29
申请人： Koji Sakui
发明人： Koji Sakui
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3427
摘要： Memory devices and methods are disclosed. An embodiment of one such method includes programming a first memory cell to a first program level by applying a first series of programming pulses to a control gate of the first memory cell, where the programming pulses of the first series have voltages that sequentially increase by a certain first voltage; and programming a second memory cell to a second program level that is higher than the first program level by applying a second series of programming pulses to a control gate of the second memory cell, where the programming pulses of the second series have voltages that sequentially increase by a certain second voltage less than the certain first voltage.
摘要翻译：公开了存储器件和方法。一种这样的方法的实施例包括通过将第一系列编程脉冲施加到第一存储器单元的控制栅极来将第一存储器单元编程为第一程序级，其中第一系列的编程脉冲具有依次增加的电压一定的第一电压; 以及通过将第二系列编程脉冲施加到所述第二存储器单元的控制栅极来将第二存储器单元编程为高于所述第一编程电平的第二编程电平，其中所述第二系列的编程脉冲具有顺序增加的电压通过一定的第二电压小于一定的第一电压。

5. 发明申请

US20140036590A1 PARTIAL BLOCK MEMORY OPERATIONS 审中-公开
标题翻译：部分块存储器操作
公开(公告)号：US20140036590A1
公开(公告)日：2014-02-06
申请号：US13564458
申请日：2012-08-01
申请人： Peter Sean Feeley , Koji Sakui , Akira Goda
发明人： Peter Sean Feeley , Koji Sakui , Akira Goda
IPC分类号： G11C16/04
摘要： Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.
摘要翻译：公开了诸如包括包含电荷存储装置串的存储器单元块的方法和装置。每个串可以包括以多层形成的多个电荷存储装置。该装置可以包括由串共享的多个接入线。多个接入线路中的每一个可以耦合到与多个层级的相应层对应的电荷存储装置。该装置可以包括与弦相关联的多个子源。多个子源中的每一个可以耦合到字符串的多个子集的相应子集的每个串的源选择门，并且每个子源可以独立地从其他子源中选择以选择字符串独立于对应于其他子集的其他字符串。

6. 发明申请

US20130336070A1 APPARATUSES AND METHODS TO MODIFY PILLAR POTENTIAL 有权
标题翻译：修改支柱潜力的装置和方法
公开(公告)号：US20130336070A1
公开(公告)日：2013-12-19
申请号：US13525035
申请日：2012-06-15
申请人： Koji Sakui , Peter Sean Feeley
发明人： Koji Sakui , Peter Sean Feeley
IPC分类号： G11C16/10 , H01L29/788
CPC分类号： G11C16/10 , G11C16/02 , G11C16/0466 , G11C16/0483
摘要： Apparatus are disclosed, such as a block including a number of strings of charge storage devices, each string including a number of charge storage devices associated with a pillar, and each pillar including semiconductor material. Methods are disclosed, such as a method that includes performing a first operation on a first charge storage device associated with a pillar in the block, modifying an electrical potential of the pillar, and performing a second operation on a second charge storage device in the block. Additional apparatus and methods are described.
摘要翻译：公开了诸如包括多个电荷存储装置串的块的每个串，包括与柱相关联的多个电荷存储装置，并且每个支柱包括半导体材料。公开了一种方法，例如包括在与块中的柱相关联的第一电荷存储装置上执行第一操作的方法，修改支柱的电位，以及对块中的第二电荷存储装置执行第二操作。描述附加的装置和方法。

7. 发明授权

US08537623B2 Devices and methods of programming memory cells 有权
标题翻译：编程存储单元的设备和方法
公开(公告)号：US08537623B2
公开(公告)日：2013-09-17
申请号：US13178217
申请日：2011-07-07
申请人： Koichi Kawai , Koji Sakui , Peter Feeley
发明人： Koichi Kawai , Koji Sakui , Peter Feeley
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C11/5628 , G11C16/10 , G11C16/3427 , G11C16/3459
摘要： Devices and methods of programming memory cells, both SLC and MLC, such as to reduce charge-storage structure to charge-storage structure coupling, are shown and described. Programming of memory cells can include comparing a first page of data to a second page of data, and further programming cells corresponding to the first page of data that will not likely be affected by coupling from programming the second page of data.
摘要翻译：显示和描述了将存储器单元（SLC和MLC）编程的设备和方法，例如将电荷存储结构减少到电荷存储结构耦合。存储器单元的编程可以包括将数据的第一页与第二页数据进行比较，以及进一步对与第一页数据相对应的编程单元，该第一页数据不会受编程第二页数据的耦合的影响。

8. 发明申请

US20130135937A1 PROGRAMMING MEMORY CELLS USING SMALLER STEP VOLTAGES FOR HIGHER PROGRAM LEVELS 有权
标题翻译：使用较小程序级电压编程存储器电池
公开(公告)号：US20130135937A1
公开(公告)日：2013-05-30
申请号：US13305795
申请日：2011-11-29
申请人： Koji Sakui
发明人： Koji Sakui
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3427
摘要： Memory devices and methods are disclosed. An embodiment of one such method includes programming a first memory cell to a first program level by applying a first series of programming pulses to a control gate of the first memory cell, where the programming pulses of the first series have voltages that sequentially increase by a certain first voltage; and programming a second memory cell to a second program level that is higher than the first program level by applying a second series of programming pulses to a control gate of the second memory cell, where the programming pulses of the second series have voltages that sequentially increase by a certain second voltage less than the certain first voltage.
摘要翻译：公开了存储装置和方法。一种这样的方法的实施例包括通过将第一系列编程脉冲施加到第一存储器单元的控制栅极来将第一存储器单元编程为第一程序级，其中第一系列的编程脉冲具有依次增加的电压一定的第一电压; 以及通过将第二系列编程脉冲施加到所述第二存储器单元的控制栅极来将第二存储器单元编程为高于所述第一编程电平的第二编程电平，其中所述第二系列的编程脉冲具有顺序增加的电压通过一定的第二电压小于一定的第一电压。

9. 发明申请

US20080212373A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH A STACKED GATE INCLUDING A FLOATING GATE AND A CONTROL GATE 失效
标题翻译：具有包括浮动门和控制门的堆叠门的半导体集成电路装置
公开(公告)号：US20080212373A1
公开(公告)日：2008-09-04
申请号：US12027744
申请日：2008-02-07
申请人： Takehiro HASEGAWA , Akira Umezawa , Koji Sakui , Fumitaka Arai , Ryo Mitani
发明人： Takehiro HASEGAWA , Akira Umezawa , Koji Sakui , Fumitaka Arai , Ryo Mitani
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： H01L27/11524 , G11C11/005 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C16/20 , H01L27/105 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11526 , H01L27/11546
摘要： A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.
摘要翻译：半导体集成电路器件包括第一和第二非易失性半导体存储器。第一存储器具有第一和第二选择晶体管和第一存储单元晶体管。第一存储单元晶体管在第一栅极绝缘膜上具有第一浮置栅极，在第一栅极间绝缘膜上具有第一控制栅极。第二存储器具有第三选择晶体管和第二存储单元晶体管。第二存储单元晶体管在第二栅极绝缘膜上具有第二浮置栅极，在第二栅极绝缘膜上具有第二控制栅极。第一和第二栅极绝缘膜具有相同的膜厚度。第一和第二浮栅具有相同的膜厚度。第一和第二栅极间绝缘膜具有相同的膜厚度。第一和第二控制栅具有相同的膜厚度。

10. 发明申请

US20080192549A1 Nonvolatile Semiconductor Storage Device and Operation Method Thereof 有权
标题翻译：非易失性半导体存储器件及其操作方法
公开(公告)号：US20080192549A1
公开(公告)日：2008-08-14
申请号：US11815387
申请日：2006-02-03
申请人： Michio Nakagawa , Koji Sakui
发明人： Michio Nakagawa , Koji Sakui
IPC分类号： G11C16/12
CPC分类号： G11C16/12 , G11C16/3468
摘要： To provide a nonvolatile semiconductor storage device and a drive method thereof capable of preventing lowering efficiency of write or erase operation and reducing the write time and the erase time. [MEANS FOR SOLVING PROBLEMS] A nonvolatile semiconductor storage device includes an electrically rewritable memory cell formed by a floating gate and a control gate layered on a semiconductor layer. The nonvolatile semiconductor storage device applies a plurality of threshold value fluctuation pulses having a stepwise high potential to the memory cell and then detects a threshold value of the memory cell. When the threshold value of the memory cell is not a predetermined value, a plurality of threshold value fluctuation pulses having stepwise high potential are applied to the memory cell from a potential of the lastly applied threshold value fluctuation pulse, among the plurality of threshold value fluctuation pulses, to which a certain potential is added.
摘要翻译：提供一种能够防止写入或擦除操作的降低效率并减少写入时间和擦除时间的非易失性半导体存储器件及其驱动方法。解决问题的手段非易失性半导体存储装置包括由浮置栅极和层叠在半导体层上的控制栅极形成的电可重写存储单元。非易失性半导体存储装置向存储单元施加具有逐级高电位的多个阈值波动脉冲，然后检测存储单元的阈值。当存储单元的阈值不是预定值时，具有逐步高电位的多个阈值波动脉冲从最近施加的阈值波动脉冲的电位在多个阈值波动之中被施加到存储单元脉冲，添加一定的电位。

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