专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08199549B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08199549B2
公开(公告)日：2012-06-12
申请号：US12859445
申请日：2010-08-19
申请人： Hiroyuki Mizuno , Takeshi Sakata , Nobuhiro Oodaira , Takao Watanabe , Yusuke Kanno
发明人： Hiroyuki Mizuno , Takeshi Sakata , Nobuhiro Oodaira , Takao Watanabe , Yusuke Kanno
IPC分类号： G11C5/06
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
摘要翻译：本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为过程波动很大程度。本发明提供以下典型的效果。在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

2. 发明授权

US08106678B2 Semiconductor integrated circuits with power reduction mechanism 失效
标题翻译：半导体集成电路具有功率降低机制
公开(公告)号：US08106678B2
公开(公告)日：2012-01-31
申请号：US12645784
申请日：2009-12-23
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K19/0016 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , H03K19/00361
摘要： A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.
摘要翻译：包括第一和第二电力线的半导体器件，以及耦合在电力线之间的第一和第二电路块。第一开关元件插入在第一电路块和至少一个电源线之间，并且第二开关元件插入在第二电路块和至少一个电源线之间。第一开关元件被导通以允许第一电路块通过第一和第二电力线接收电力电压，而第二开关元件变得不导通，以防止第二电路块通过第一和第二电力接收电力电压使得流过第二电路的漏电流被抑制。

3. 发明授权

US07881088B2 Content addressable memory device 有权
标题翻译：内容可寻址存储设备
公开(公告)号：US07881088B2
公开(公告)日：2011-02-01
申请号：US12367108
申请日：2009-02-06
申请人： Satoru Hanzawa , Takeshi Sakata , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Takeshi Sakata , Kazuhiko Kajigaya
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.
摘要翻译：有效存储范围指定的IP地址，以减少必要条目的数量，从而提高TCAM的存储容量。本发明的代表性手段是：存储信息（条目）和输入信息（比较信息或搜索关键字）是公共块码，使得任何位必须是逻辑值“1”; 匹配线是分层结构的，并且存储器单元被布置在多个子匹配线和多条搜索线的交叉点处; 此外，子匹配线分别通过子匹配检测器连接到主匹配线，并且主匹配检测器被布置在主匹配线上。

4. 发明申请

US20100188877A1 Storage device 审中-公开
标题翻译：储存设备
公开(公告)号：US20100188877A1
公开(公告)日：2010-07-29
申请号：US12659984
申请日：2010-03-26
申请人： Satoru Hanzawa , Kiyoo Itoh , Hideyuki Matsuoka , Motoyasu Terao , Takeshi Sakata
发明人： Satoru Hanzawa , Kiyoo Itoh , Hideyuki Matsuoka , Motoyasu Terao , Takeshi Sakata
IPC分类号： G11C5/06
CPC分类号： H01L27/101 , G11C7/12 , G11C8/10 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/0054 , G11C2013/0078 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
摘要翻译：本发明的目的是避免在由存储器单元组成的存储器阵列中驱动未选择的数据线，每个存储器单元在选择的字线上的所有存储单元中的选择晶体管时根据可变电阻使用存储元件和选择晶体管进行。为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。

5. 发明授权

US07636808B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07636808B2
公开(公告)日：2009-12-22
申请号：US10790880
申请日：2004-03-03
申请人： Satoru Akiyama , Takeshi Sakata , Takao Watanabe
发明人： Satoru Akiyama , Takeshi Sakata , Takao Watanabe
IPC分类号： G06F12/08 , G11C8/00
CPC分类号： G06F12/0804 , G06F12/0864 , G06F12/0893 , G06F2212/2024
摘要： A semiconductor device employs a SESO memory or a phase change memory which has a smaller memory cell area than SRAM. The semiconductor device has a plurality of memory banks each composed of the SESO or phase change memories, and a cache memory which has a number of ways equal to the ratio of a write speed (m) to a read speed (n). The semiconductor device controls the cache memory such that a write back operation is not repeated on the same memory bank.
摘要翻译：半导体器件采用具有比SRAM更小的存储单元面积的SESO存储器或相变存储器。半导体器件具有各自由SESO或相变存储器构成的多个存储体，以及高速缓冲存储器，其具有等于写入速度（m）与读取速度（n）的比例的多个方式。半导体器件控制高速缓冲存储器，使得在相同的存储体上不重复写回操作。

6. 发明授权

US07622766B2 Semiconductor memory device and method for producing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07622766B2
公开(公告)日：2009-11-24
申请号：US11808228
申请日：2007-06-07
申请人： Tomoyuki Ishii , Taro Osabe , Hideaki Kurata , Takeshi Sakata
发明人： Tomoyuki Ishii , Taro Osabe , Hideaki Kurata , Takeshi Sakata
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , B82Y10/00 , G11C11/5621 , G11C11/5671 , G11C16/0433 , G11C16/0458 , G11C16/0475 , G11C16/0491 , G11C2216/06 , H01L27/115 , H01L27/11521
摘要： Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 μm, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.
摘要翻译：公开了使用设置在半导体衬底上的反转层作为数据线的非易失性半导体存储器件。存储器件可以减少存储器单元之间的特性变化并且可以降低位成本。多个辅助栅极通过栅极氧化膜形成在p型阱的上部。在覆盖这些辅助栅极的层间绝缘体的上部形成用作控制电极的字线。这些字线的宽度例如为0.1μm，并且每个字线通过作为厚度为约20nm的氧化硅膜的侧壁间隔物与其相邻字线分开。

7. 发明申请

US20090212026A1 WIRE ELECTRIC DISCHARGE MACHINING METHOD, SEMICONDUCTOR WAFER MANUFACTURING METHOD, AND SOLAR BATTERY CELL MANUFACTURING METHOD 有权
标题翻译：电线放电加工方法，半导体制造方法和太阳能电池组件制造方法
公开(公告)号：US20090212026A1
公开(公告)日：2009-08-27
申请号：US12093836
申请日：2005-11-16
申请人： Tatsushi Sato , Yoshihito Imai , Teiji Takahashi , Takeshi Sakata , Tomoko Sendai , Yoichiro Nishimoto , Shigeru Matsuno , Takeyuki Maegawa , Takaaki Iwata
发明人： Tatsushi Sato , Yoshihito Imai , Teiji Takahashi , Takeshi Sakata , Tomoko Sendai , Yoichiro Nishimoto , Shigeru Matsuno , Takeyuki Maegawa , Takaaki Iwata
IPC分类号： B23H1/00
CPC分类号： B23H7/02 , B23H9/00
摘要： Provided are a wire electric discharge machining method for poorly conductive materials, such as solar cell silicon, and a semiconductor wafer manufacturing method and a solar battery cell manufacturing method based on the wire electric discharge machining method. Electrical discharge machining of a high volume resistivity, hard and brittle materials, having a volume resistivity that is equal to or higher than 0.5 Ω·cm and equal to or lower than 5 Ω·cm is performed by applying a pulse voltage having a pulse width that is equal to or higher than 1 μsec and equal to or lower than 4 μsec and having a peak current at the time of machining a wire electrode that is equal to or higher than 10A and equal to or lower than 50A to a wire electrode and generating a discharge pulse between the wire electrode and a subject to be machined.
摘要翻译：本发明提供一种导电材料的导电放电加工方法，例如太阳能电池硅，半导体晶片的制造方法以及基于该放电加工方法的太阳能电池单元的制造方法。通过施加具有脉冲宽度的脉冲电压来执行体积电阻率等于或高于0.5Ω·cm且等于或小于5Ω·cm的高体积电阻率，硬脆性材料的放电加工等于或高于1个音箱并且等于或低于4个音箱，并且在对线电极进行等于或高于10A且等于或小于50A的线电极加工时具有峰值电流，以及在线电极和待加工对象之间产生放电脉冲。

8. 发明授权

US07542357B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07542357B2
公开(公告)日：2009-06-02
申请号：US11785553
申请日：2007-04-18
申请人： Takeshi Sakata , Kenichi Osada , Riichiro Takemura , Hideyuki Matsuoka
发明人： Takeshi Sakata , Kenichi Osada , Riichiro Takemura , Hideyuki Matsuoka
IPC分类号： G11C7/10
CPC分类号： G11C13/0004 , G11C8/06 , G11C8/10 , G11C13/0069 , G11C2213/79
摘要： A phase change memory is provided with a write data register, an output data selector, a write address register, an address comparator and a flag register. Write data is not only written into a memory cell but also retained by the write data register until the next write cycle. If a read access occurs to that address before the next write cycle, data is read out from the register without reading the data from the memory cell array. Without elongating the cycle time, it is possible not only to use a long time to write data into a memory cell therein but also to make longer the interval between the time when a write operation is done and the time when the subsequent read operation is made from that memory cell. As a result, data can be written reliably.
摘要翻译：相变存储器具有写入数据寄存器，输出数据选择器，写入地址寄存器，地址比较器和标志寄存器。写数据不仅写入存储单元，而且由写数据寄存器保留，直到下一个写周期。如果在下一个写周期之前对该地址进行读取访问，则从寄存器读出数据，而不从存储单元阵列中读取数据。在不延长循环时间的情况下，不仅可以长时间地将数据写入其中的存储单元，而且可以使写操作完成的时间与后续读操作的时间之间的间隔更长从该记忆单元。因此，可以可靠地写入数据。

9. 发明申请

US20090122602A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
标题翻译：半导体集成电路设备
公开(公告)号：US20090122602A1
公开(公告)日：2009-05-14
申请号：US12352668
申请日：2009-01-13
申请人： RIICHIRO TAKEMURA , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
发明人： RIICHIRO TAKEMURA , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
IPC分类号： G11C11/00 , G11C8/08 , G11C7/00
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
摘要翻译：实现了高集成度和高速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。在写入驱动器中提供锁存器。通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活的预充电信号。由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。

10. 发明申请

US20080309369A1 SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM 失效
标题翻译：具有功率降低机制的半导体集成电路
公开(公告)号：US20080309369A1
公开(公告)日：2008-12-18
申请号：US12133969
申请日：2008-06-05
申请人： Takeshi SAKATA , Kiyoo ITOH , Masashi HORIGUCHI
发明人： Takeshi SAKATA , Kiyoo ITOH , Masashi HORIGUCHI
IPC分类号： H03K19/003 , G05F1/10
CPC分类号： H03K19/0016 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , H03K19/00361
摘要： A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.
摘要翻译：包括第一和第二电力线的半导体器件，以及耦合在电力线之间的第一和第二电路块。第一开关元件插入在第一电路块和至少一个电源线之间，并且第二开关元件插入在第二电路块和至少一个电源线之间。第一开关元件被导通以允许第一电路块通过第一和第二电力线接收电力电压，而第二开关元件变得不导通，以防止第二电路块通过第一和第二电力接收电力电压使得流过第二电路的漏电流被抑制。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式