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    • 6. 发明授权
    • Non-volatile memory and the fabrication method
    • 非易失性存储器及其制造方法
    • US07394090B2
    • 2008-07-01
    • US11798364
    • 2007-05-14
    • Kiyoyuki MoritaNoboru YamadaAkihito MiyamotoTakashi OhtsukaHideyuki Tanaka
    • Kiyoyuki MoritaNoboru YamadaAkihito MiyamotoTakashi OhtsukaHideyuki Tanaka
    • H01L47/00
    • G11C13/0004G11C14/009H01L27/1104H01L27/24H01L45/04H01L45/145
    • A non-volatile memory comprising: a first substrate (100) and a second substrate (110), the first substrate (100) having a plurality of switching elements (4) arranged in matrix, and a plurality of first electrodes (18) connected to the switching element (4), the second substrate (110) having a conductive film (32), and a recording layer (34) whose resistance value changes by application of an electric pulse, wherein the plurality of first electrodes (18) are integrally covered by the recording layer (34), the recording layer (34) thereby being held between the plurality of first electrodes (18) and the conductive film (32); the first substrate (100) further comprising a second electrode (22), the second electrode (22) being electrically connected to the conductive film (32), the voltage of which is maintained at a set level while applying current to the recording layer (34). This non-volatile memory achieves high integration at low cost.
    • 一种非易失性存储器,包括:第一基板(100)和第二基板(110),所述第一基板(100)具有布置成矩阵的多个开关元件(4),并且多个第一电极(18)被连接 至所述开关元件(4),所述第二基板(110)具有导电膜(32)以及其电阻值通过施加电脉冲而改变的记录层(34),其中所述多个第一电极(18)为 由记录层(34)整体覆盖,记录层(34)由此保持在多个第一电极(18)和导电膜(32)之间; 所述第一基板(100)还包括第二电极(22),所述第二电极(22)电连接到所述导电膜(32),其电压保持在设定电平,同时向所述记录层施加电流( 34)。 这种非易失性存储器以低成本实现高集成度。
    • 7. 发明申请
    • Non-volatile memory and the fabrication method
    • 非易失性存储器及其制造方法
    • US20070210362A1
    • 2007-09-13
    • US11798364
    • 2007-05-14
    • Kiyoyuki MoritaNoboru YamadaAkihito MiyamotoTakashi OhtsukaHideyuki Tanaka
    • Kiyoyuki MoritaNoboru YamadaAkihito MiyamotoTakashi OhtsukaHideyuki Tanaka
    • H01L27/11
    • G11C13/0004G11C14/009H01L27/1104H01L27/24H01L45/04H01L45/145
    • A non-volatile memory comprising: a first substrate (100) and a second substrate (110), the first substrate (100) having a plurality of switching elements (4) arranged in matrix, and a plurality of first electrodes (18) connected to the switching element (4), the second substrate (110) having a conductive film (32), and a recording layer (34) whose resistance value changes by application of an electric pulse, wherein the plurality of first electrodes (18) are integrally covered by the recording layer (34), the recording layer (34) thereby being held between the plurality of first electrodes (18) and the conductive film (32); the first substrate (100) further comprising a second electrode (22), the second electrode (22) being electrically connected to the conductive film (32), the voltage of which is maintained at a set level while applying current to the recording layer (34). This non-volatile memory achieves high integration at low cost.
    • 一种非易失性存储器,包括:第一基板(100)和第二基板(110),所述第一基板(100)具有布置成矩阵的多个开关元件(4),并且多个第一电极(18)被连接 至所述开关元件(4),所述第二基板(110)具有导电膜(32)以及其电阻值通过施加电脉冲而改变的记录层(34),其中所述多个第一电极(18)为 由记录层(34)整体覆盖,记录层(34)由此保持在多个第一电极(18)和导电膜(32)之间; 所述第一基板(100)还包括第二电极(22),所述第二电极(22)电连接到所述导电膜(32),其电压保持在设定电平,同时向所述记录层施加电流( 34)。 这种非易失性存储器以低成本实现高集成度。
    • 9. 发明授权
    • Non-volatile flip flop
    • 非易失性触发器
    • US07206217B2
    • 2007-04-17
    • US10754058
    • 2004-01-09
    • Takashi OhtsukaHideyuki Tanaka
    • Takashi OhtsukaHideyuki Tanaka
    • G11C11/40
    • G11C14/0072G11C8/16G11C13/0004G11C14/009H01L21/28291H01L27/101H01L27/11H03K3/356008
    • A non-volatile flip flop according to the invention comprising: a flip flop section (4) having a pair of memory nodes (5, 6) for storing a pair of inverse logic data elements; and a pair of non-volatile resistance change elements (11, 12) which are connected to the pair of memory nodes (5, 6) through switching elements (9, 10) respectively and the resistances of which vary so as to be retainable, wherein, in a store operation, the resistances of the pair of non-volatile resistance change elements (11, 12) can be varied according to the respective potentials of the pair of memory nodes (5, 6) and, in a recall operation, the pair of memory nodes (5, 6) can be placed at potentials respectively according to the difference in resistance between the pair of non-volatile resistance change elements (11, 12).
    • 根据本发明的非易失性触发器包括:触发器部分(4),具有用于存储一对反逻辑数据元素的一对存储器节点(5,6); 以及一对非易失性电阻变化元件(11,12),它们分别通过开关元件(9,10)连接到一对存储器节点(5,6),并且其电阻变化以便保持, 其特征在于,在存储操作中,所述一对非易失性电阻变化元件(11,12)的电阻可以根据所述一对存储器节点(5,6)的各自的电位而变化,并且在回调操作中, 可以根据所述一对非易失性电阻变化元件(11,12)之间的电阻差分别将所述一对存储器节点(5,6)置于电位上。
    • 10. 发明申请
    • Nonvolatile flip-flop circuit and method of driving the same
    • 非易失性触发电路及其驱动方法
    • US20050206421A1
    • 2005-09-22
    • US11080454
    • 2005-03-16
    • Takashi NishikawaKenji ToyodaTakashi Ohtsuka
    • Takashi NishikawaKenji ToyodaTakashi Ohtsuka
    • G11C11/22H03K3/356H03K3/289
    • H03K3/356008G11C11/22
    • The present invention provides a method of driving a nonvolatile flip-flop circuit comprising the following steps of: a data hold step of holding an input data signal D utilizing polarization of a ferroelectric material of a ferroelectric gate transistor (601) when the data signal D is input while a first clocked inverter (604), a second clocked inverter (603), and a third switching element (602) are turned on and a first switching element (605), a second switching element (607), and a third clocked inverter (608) are turned off; and a data output step of outputting an output signal Q (−Q) based on the held data signal D placing the first clocked inverter (604), the second clocked inverter (603), and the third switching element (602) in the OFF state and placing the first switching element (605), the second switching element (607), and the third clocked inverter (608) in the ON state so as to interrupt an input of a data signal and maintain a polarization state of the ferroelectric material of the ferroelectric gate transistor (601).
    • 本发明提供了一种驱动非易失性触发电路的方法,包括以下步骤:数据保持步骤,当数据信号D(D)被利用时,利用铁电栅极晶体管(601)的铁电材料的极化来保持输入数据信号D 在第一时钟反相器(604),第二时钟反相器(603)和第三开关元件(602)导通时,第一开关元件(605),第二开关元件(607)和第三开关元件 时钟反相器(608)关闭; 以及数据输出步骤,基于将第一时钟反相器(604),第二时钟反相器(603)和第三开关元件(602)放置在OFF中的保持数据信号D输出输出信号Q(-Q) 状态,并且将第一开关元件(605),第二开关元件(607)和第三时钟反相器(608)置于导通状态,以便中断数据信号的输入并保持铁电材料的极化状态 的铁电栅极晶体管(601)。