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1. 发明授权

US09047079B2 Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition 有权
标题翻译：当竞争性指令完成执行以确保安全的共享资源状况时，指示禁用线程到其他线程
公开(公告)号：US09047079B2
公开(公告)日：2015-06-02
申请号：US13435123
申请日：2012-03-30
申请人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
发明人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
IPC分类号： G06F9/46 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/3857 , G06F9/3889
摘要： A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.
摘要翻译：用于指示关于被禁用线程的安全共享资源状况的技术提供了一种用于向其他硬件线程提供快速指示的机制，临时禁用的线程不再影响共享资源，例如共享专用寄存器和翻译查找，处理器核心内的缓冲区。来自核心内的流水线的信号表示流水线中的任何待执行的任何指示是否影响共享资源，如果没有，则通过线程状态寄存器中的状态更改将线程禁用状态呈现给其他线程。在接收到特定硬件线程被禁用的指示时，控制逻辑停止对特定硬件线程的指令的分派，然后等待直到由指令影响共享资源的任何指示已经被清除。然后控制逻辑更新线程状态以指示线程被禁用。

2. 发明申请

US20140075441A1 METHOD AND APPARATUS FOR RECORDING AND PROFILING TRANSACTION FAILURE SOURCE ADDRESSES IN HARDWARE TRANSACTIONAL MEMORIES 有权
标题翻译：硬件交易记录中记录和分类交易失败源地址的方法和装置
公开(公告)号：US20140075441A1
公开(公告)日：2014-03-13
申请号：US13615416
申请日：2012-09-13
申请人： Robert J. Blainey , Harold W. Cain , Susan E. Eisen , Bradly G. Frey , Charles B. Hall , Hung Q. Le , Cathy May
发明人： Robert J. Blainey , Harold W. Cain , Susan E. Eisen , Bradly G. Frey , Charles B. Hall , Hung Q. Le , Cathy May
IPC分类号： G06F9/46
CPC分类号： G06F9/467 , G06F11/1474 , G06F11/36 , G06F11/3648
摘要： A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.
摘要翻译：处理器核心包括事务存储器，事务失败指令地址寄存器（TFIAR）和事务故障数据地址寄存器（TFDAR）。事务存储器存储由处理器核心执行的多个事务的信息。处理器核心分别从TFIAR和TFDAR检索与中止事务相关联的指令和数据地址，并将它们存储到一个概要分析表中。然后，处理器核心基于与中止事务相关联的指令和数据地址生成分析信息。

3. 发明授权

US08544022B2 Transactional memory preemption mechanism 失效
标题翻译：事务记忆抢占机制
公开(公告)号：US08544022B2
公开(公告)日：2013-09-24
申请号：US13465115
申请日：2012-05-07
申请人： Richard L. Arndt , Harold W. Cain, III , Bradly G. Frey , Cathy May
发明人： Richard L. Arndt , Harold W. Cain, III , Bradly G. Frey , Cathy May
IPC分类号： G06F9/46 , G06F15/00 , G06F11/00 , G06F13/24
CPC分类号： G06F9/466 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863
摘要： Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.
摘要翻译：提供了在数据处理系统中执行事务的机制。在处理器的内部寄存器中生成事务检查点数据结构。事务检查点数据结构存储表示执行相应事务之前的时间的程序寄存器的状态的事务检查点数据。执行包括由处理器执行的代码的第一部分的事务。在执行事务时接收事务的中断，结果，事务检查点数据被存储到数据处理系统的存储器中的数据结构。然后执行第二部分代码。响应于发生的事件导致处理器的执行切换返回到事务的执行，使用数据处理系统的存储器中的数据结构恢复程序寄存器的状态。

4. 发明授权

US08176254B2 Specifying an access hint for prefetching limited use data in a cache hierarchy 失效
标题翻译：指定在缓存层次结构中预取有限使用数据的访问提示
公开(公告)号：US08176254B2
公开(公告)日：2012-05-08
申请号：US12424681
申请日：2009-04-16
申请人： Bradly G. Frey , Guy L. Guthrie , Cathy May , Balaram Sinharoy , Peter K. Szwed
发明人： Bradly G. Frey , Guy L. Guthrie , Cathy May , Balaram Sinharoy , Peter K. Szwed
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/6028
摘要： A system and method for specifying an access hint for prefetching limited use data. A processing unit receives a data cache block touch (DCBT) instruction having an access hint indicating to the processing unit that a program executing on the data processing system may soon access a cache block addressed within the DCBT instruction. The access hint is contained in a code point stored in a subfield of the DCBT instruction. In response to detecting that the code point is set to a specific value, the data addressed in the DCBT instruction is prefetched into an entry in the lower level cache. The entry may then be updated as a least recently used entry of a plurality of entries in the lower level cache. In response to a new cache block being fetched to the cache, the prefetched cache block is cast out of the cache.
摘要翻译：一种用于指定预取有限使用数据的访问提示的系统和方法。处理单元接收具有指示给处理单元的访问提示的数据高速缓存块触摸（DCBT）指令，即在数据处理系统上执行的程序可以很快访问在DCBT指令内寻址的高速缓存块。访问提示包含在存储在DCBT指令的子字段中的代码点中。响应于检测到代码点被设置为特定值，DCBT指令中寻址的数据被预取到低级缓存中的条目中。然后可以将条目作为较低级别高速缓存中的多个条目的最近最少使用的条目来更新。响应于将新的高速缓存块提取到高速缓存，预取的高速缓存块被抛出高速缓存。

5. 发明申请

US20090276605A1 Retaining an Association Between a Virtual Address Based Buffer and a User Space Application that Owns the Buffer 失效
标题翻译：保留基于虚拟地址的缓冲区和拥有缓冲区的用户空间应用程序之间的关联
公开(公告)号：US20090276605A1
公开(公告)日：2009-11-05
申请号：US12114945
申请日：2008-05-05
申请人： Richard L. Arndt , Aaron C. Brown , Bradly G. Frey , Gregory F. Pfister , Renato J. Recio , Steven M. Thurber
发明人： Richard L. Arndt , Aaron C. Brown , Bradly G. Frey , Gregory F. Pfister , Renato J. Recio , Steven M. Thurber
IPC分类号： G06F12/00
CPC分类号： G06F12/0646
摘要： Registering memory space for an application is performed. One or more open calls are received from an application to access one or more input/output (I/O) devices. Responsive to receiving the one or more open calls, one or more I/O map and pin calls are sent in order to register memory space for the one or more I/O devices within at least one storage area that will be accessed by the application. A verification is made as to whether the memory space to be registered is associated with the application. Responsive to the memory space being associated with the application, at least one virtual I/O bus address is received for each registered memory space of the one or more I/O devices. At least one I/O command is executed using the at least one virtual I/O bus address without intervention by an operating system or operating system image.
摘要翻译：注册应用程序的内存空间。从应用程序接收一个或多个打开的呼叫以访问一个或多个输入/输出（I / O）设备。响应于接收一个或多个开放呼叫，发送一个或多个I / O映射和引脚呼叫，以便为将由应用程序访问的至少一个存储区域内的一个或多个I / O设备注册存储器空间。验证要注册的存储空间是否与应用程序相关联。响应于与应用相关联的存储器空间，对于一个或多个I / O设备的每个已注册的存储器空间接收至少一个虚拟I / O总线地址。使用至少一个虚拟I / O总线地址执行至少一个I / O命令，而无需操作系统或操作系统映像的干预。

6. 发明授权

US09626187B2 Transactional memory system supporting unbroken suspended execution 有权
公开(公告)号：US09626187B2
公开(公告)日：2017-04-18
申请号：US12788351
申请日：2010-05-27
申请人： Harold W. Cain, III , Bradly G. Frey , Benjamin Herrenschmidt , Hung Q. Le , Cathy May , Maged M. Michael , Jose E. Moreira , Priya A. Nagpurkar , Naresh Nayar , Randal C. Swanberg
发明人： Harold W. Cain, III , Bradly G. Frey , Benjamin Herrenschmidt , Hung Q. Le , Cathy May , Maged M. Michael , Jose E. Moreira , Priya A. Nagpurkar , Naresh Nayar , Randal C. Swanberg
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30 , G06F9/46 , G06F9/38
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/30189 , G06F9/3834 , G06F9/3842 , G06F9/3859 , G06F9/3863 , G06F9/3865 , G06F9/467
摘要： Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.

7. 发明申请

US20140013060A1 ENSURING CAUSALITY OF TRANSACTIONAL STORAGE ACCESSES INTERACTING WITH NON-TRANSACTIONAL STORAGE ACCESSES 有权
公开(公告)号：US20140013060A1
公开(公告)日：2014-01-09
申请号：US13543325
申请日：2012-07-06
申请人： Bradly G. Frey , Cathy May , Derek E. Williams
发明人： Bradly G. Frey , Cathy May , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F9/466 , G06F12/0813 , G06F12/0831
摘要： A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction.

8. 发明申请

US20130232320A1 PERSISTENT PREFETCH DATA STREAM SETTINGS 有权
标题翻译：数据预处理数据流设置
公开(公告)号：US20130232320A1
公开(公告)日：2013-09-05
申请号：US13410260
申请日：2012-03-01
申请人： JASON N. DALE , MILES R. DOOLEY , RICHARD J. EICKEMEYER , BRADLY G. FREY , YAOQING GAO , FRANCIS P. O'CONNELL , JEFFREY A. STUECHELI
发明人： JASON N. DALE , MILES R. DOOLEY , RICHARD J. EICKEMEYER , BRADLY G. FREY , YAOQING GAO , FRANCIS P. O'CONNELL , JEFFREY A. STUECHELI
IPC分类号： G06F15/82 , G06F9/312 , G06F9/30
CPC分类号： G06F12/0862 , G06F9/383 , G06F2212/6028
摘要： A prefetch unit includes a transience register and a length register. The transience register hosts an indication of transient for data stream prefetching. The length register hosts an indication of a stream length for data stream prefetching. The prefetch unit monitors the transience register and the length register. The prefetch unit generates prefetch requests of data streams with a transient property up to the stream length limit when the transience register indicates transient and the length register indicates the stream length limit for data stream prefetching. A cache controller coupled with the prefetch unit implements a cache replacement policy and cache coherence protocols. The cache controller writes data supplied from memory responsive to the prefetch requests into cache with an indication of transient. The cache controller victimizes cache lines with an indication of transient independent of the cache replacement policy.
摘要翻译：预取单元包括一个过渡寄存器和一个长度寄存器。 Transient寄存器容纳数据流预取的瞬态指示。长度寄存器托管用于数据流预取的流长度的指示。预取单元监视临时寄存器和长度寄存器。当Transient寄存器指示瞬态时，预取单元产生具有直到流长度限制的瞬态特性的数据流的预取请求，并且长度寄存器指示数据流预取的流长度限制。与预取单元耦合的高速缓存控制器实现高速缓存替换策略和高速缓存一致性协议。高速缓存控制器将响应于预取请求的从存储器提供的数据写入高速缓存中，并显示瞬时信号。高速缓存控制器使高速缓存行受到与缓存替换策略无关的暂态指示。

9. 发明授权

US09619345B2 Apparatus for determining failure context in hardware transactional memories 有权
公开(公告)号：US09619345B2
公开(公告)日：2017-04-11
申请号：US13615241
申请日：2012-09-13
申请人： Harold W Cain , Bradly G Frey , Hung Q Le , Cathy May
发明人： Harold W Cain , Bradly G Frey , Hung Q Le , Cathy May
IPC分类号： G06F11/14 , G06F11/07 , G06F9/46
CPC分类号： G06F11/1474 , G06F9/466 , G06F9/467 , G06F11/073 , G06F11/0778
摘要： A processor core includes a transactional memory that stores information corresponding to a plurality of transactions executed by the processor core, and a transaction diagnostic register. The processor core retrieves context summary information from at least one register of the processor core. The processor core stores the context summary information of aborted transactions into the transactional memory or the transaction diagnostic register. The context summary information can be used for diagnosing the aborted transactions.

10. 发明授权

US09268598B2 Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories 有权
标题翻译：记录和分析交易失败源地址和对应于硬件事务存储器中止事务的地址的有效性指示符
公开(公告)号：US09268598B2
公开(公告)日：2016-02-23
申请号：US13615416
申请日：2012-09-13
申请人： Robert J. Blainey , Harold W. Cain , Susan E. Eisen , Bradly G. Frey , Charles B. Hall , Hung Q. Le , Cathy May
发明人： Robert J. Blainey , Harold W. Cain , Susan E. Eisen , Bradly G. Frey , Charles B. Hall , Hung Q. Le , Cathy May
IPC分类号： G06F9/46 , G06F11/14 , G06F11/36
CPC分类号： G06F9/467 , G06F11/1474 , G06F11/36 , G06F11/3648
摘要： A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.
摘要翻译：处理器核心包括事务存储器，事务失败指令地址寄存器（TFIAR）和事务故障数据地址寄存器（TFDAR）。事务存储器存储由处理器核心执行的多个事务的信息。处理器核心分别从TFIAR和TFDAR检索与中止事务相关联的指令和数据地址，并将它们存储到一个概要分析表中。然后，处理器核心基于与中止事务相关联的指令和数据地址生成分析信息。

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