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1. 发明授权

US10067765B2 Speeding up younger store instruction execution after a sync instruction 有权
公开(公告)号：US10067765B2
公开(公告)日：2018-09-04
申请号：US13470386
申请日：2012-05-14
申请人： Susan E. Eisen , Hung Q. Le , Bryan J. Lloyd , Dung Q. Nguyen , David S. Ray , Benjamin W. Stolt , Shih-Hsiung S. Tung
发明人： Susan E. Eisen , Hung Q. Le , Bryan J. Lloyd , Dung Q. Nguyen , David S. Ray , Benjamin W. Stolt , Shih-Hsiung S. Tung
IPC分类号： G06F9/38 , G06F9/30
摘要： Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

2. 发明申请

US20130305022A1 Speeding Up Younger Store Instruction Execution after a Sync Instruction 审中-公开
标题翻译：加快同步指令后的较小的存储指令执行
公开(公告)号：US20130305022A1
公开(公告)日：2013-11-14
申请号：US13470386
申请日：2012-05-14
申请人： Susan E. Eisen , Hung Q. Le , Bryan J. Lloyd , Dung Q. Nguyen , David S. Ray , Benjamin W. Stolt , Shih-Hsiung S. Tung
发明人： Susan E. Eisen , Hung Q. Le , Bryan J. Lloyd , Dung Q. Nguyen , David S. Ray , Benjamin W. Stolt , Shih-Hsiung S. Tung
IPC分类号： G06F9/312
CPC分类号： G06F9/30087 , G06F9/3824 , G06F9/3834 , G06F9/3857 , G06F9/3861
摘要： Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.
摘要翻译：在处理器中提供用于执行比先前调度的同步（sync）指令更年轻的指令的机制。处理器的指令定序器单元调度同步指令。同步指令被发送到处理器外部的一个或多个设备的嵌套。指令定序器单元在调度同步指令之后调度后续指令。调度同步指令后的后续指令的调度是在收到来自嵌套的同步确认响应之前执行的。指令定序器单元基于后续指令的完成是否依赖于从嵌套接收到同步确认和完成同步指令而执行后续指令的完成。

3. 发明授权

US08086801B2 Loading data to vector renamed register from across multiple cache lines 有权
标题翻译：从多个缓存行将数据加载到向量重命名的寄存器
公开(公告)号：US08086801B2
公开(公告)日：2011-12-27
申请号：US12420118
申请日：2009-04-08
申请人： David A. Hrusecky , David S. Ray , Bruce J. Ronchetti , Shih-Hsiung S. Tung
发明人： David A. Hrusecky , David S. Ray , Bruce J. Ronchetti , Shih-Hsiung S. Tung
IPC分类号： G06F13/00
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F12/0886
摘要： A load instruction that accesses data cache may be off natural alignment, which causes a cache line crossing to complete the access. The illustrative embodiments provide a mechanism for loading data across multiple cache lines without the need for an accumulation register or collection point for partial data access from a first cache line while waiting for a second cache line to be accessed. Because the accesses to separate cache lines are concatenated within the vector rename register without the need for an accumulator, an off-alignment load instruction is completely pipeline-able and flushable with no cleanup consequences.
摘要翻译：访问数据高速缓存的加载指令可能是自然对齐，这导致高速缓存行交叉以完成访问。说明性实施例提供了用于在多个高速缓存线之间加载数据的机制，而不需要在等待第二高速缓存行被访问的同时从第一高速缓存行部分数据存取的累加寄存器或收集点。因为对分离的高速缓存行的访问在矢量重命名寄存器中连接，而不需要累加器，所以非对齐加载指令是完全可管理的并且可以刷新而没有清除后果。

4. 发明申请

US20100262781A1 Loading Data to Vector Renamed Register From Across Multiple Cache Lines 有权
标题翻译：将数据加载到多个缓存行中向量重命名的注册表
公开(公告)号：US20100262781A1
公开(公告)日：2010-10-14
申请号：US12420118
申请日：2009-04-08
申请人： David A. Hrusecky , David S. Ray , Bruce J. Ronchetti , Shih-Hsiung S. Tung
发明人： David A. Hrusecky , David S. Ray , Bruce J. Ronchetti , Shih-Hsiung S. Tung
IPC分类号： G06F12/08
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F12/0886
摘要： A load instruction that accesses data cache may be off natural alignment, which causes a cache line crossing to complete the access. The illustrative embodiments provide a mechanism for loading data across multiple cache lines without the need for an accumulation register or collection point for partial data access from a first cache line while waiting for a second cache line to be accessed. Because the accesses to separate cache lines are concatenated within the vector rename register without the need for an accumulator, an off-alignment load instruction is completely pipeline-able and flushable with no cleanup consequences.
摘要翻译：访问数据高速缓存的加载指令可能是自然对齐，这导致高速缓存行交叉以完成访问。说明性实施例提供了用于在多个高速缓存线之间加载数据的机制，而不需要在等待第二高速缓存行被访问的同时从第一高速缓存行部分数据存取的累加寄存器或收集点。因为对分离的高速缓存行的访问在矢量重命名寄存器中连接，而不需要累加器，所以非对齐加载指令是完全可管理的并且可以刷新而没有清除后果。

5. 发明授权

US07949859B2 Mechanism for avoiding check stops in speculative accesses while operating in real mode 失效
标题翻译：在实模式下运行时避免检测停止的机制
公开(公告)号：US07949859B2
公开(公告)日：2011-05-24
申请号：US12043747
申请日：2008-03-06
申请人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
发明人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
IPC分类号： G06F9/00
CPC分类号： G06F9/3861 , G06F9/30189 , G06F9/383 , G06F9/3842
摘要： A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.
摘要翻译：一种用于避免投机访问中检查停止的方法和处理器。执行单元，例如加载/存储单元，可以被耦合到被配置为存储指令的队列。耦合到执行单元的寄存器可被配置为存储对应于物理存储器中的地址的值。当处理器以实模式运行时，执行单元可以检索存储在寄存器中的值。在执行单元从队列接收诸如推测性加载指令的推测性指令之后，可以确定推测指令的地址是否在检索值以下。如果推测指令的地址处于或低于该值，则执行单元可以安全地推测性地执行该指令，同时避免检查停止，因为已知存在于该物理存储器中的所有地址或低于该值的地址。

6. 发明授权

US5319761A Directory look-aside table for a virtual storage system including means for minimizing synonym entries 失效
标题翻译：用于虚拟存储系统的目录查看表，包括用于最小化同义词条目的装置
公开(公告)号：US5319761A
公开(公告)日：1994-06-07
申请号：US744203
申请日：1991-08-12
申请人： Kevin A. Chiarot , Richard J. Schmalz , Theodore J. Schmitt , Arnold S. Tran , Shih-Hsiung S. Tung
发明人： Kevin A. Chiarot , Richard J. Schmalz , Theodore J. Schmitt , Arnold S. Tran , Shih-Hsiung S. Tung
IPC分类号： G06F12/08 , G06F12/10 , G06F13/00
CPC分类号： G06F12/1036
摘要： An improved DLAT structure distinguishes between address spaces and data spaces. The DLAT structure classifies data spaces by one or more space identifications which control assignment of virtual page addresses to DLAT rows. In one embodiment, a "private space bit" is used to select different DLAT addressing algorithms. In another embodiment, data spaces are sub-classified using space identification bits, and for each sub-class, a unique algorithm is selected based on the page address bits. An Exclusive OR function is used to generate the DLAT selection bits. This approach minimizes private space synonyms while maximizing common space synonyms. The result is improved performance since the former minimizes thrashing and the latter maximizes the value of the DLAT common bit.
摘要翻译：改进的DLAT结构区分地址空间和数据空间。 DLAT结构将数据空间分类为一个或多个空间标识，这些空间标识控制虚拟页面地址的分配到DLAT行。在一个实施例中，使用“专用空间位”来选择不同的DLAT寻址算法。在另一个实施例中，使用空间识别位对数据空间进行子分类，并且对于每个子类，基于页地址位来选择唯一的算法。使用异或功能来产生DLAT选择位。这种方法最大限度地减少了私有空间同义词，同时最大化了公共空间同义词。结果是改进的性能，因为前者使抖动最小化，后者使DLAT公共位的值最大化。

7. 发明申请

US20090193233A1 Mechanism for Avoiding Check Stops in Speculative Accesses While Operating in Real Mode 失效
标题翻译：在实模式下操作时避免检测停止的机制
公开(公告)号：US20090193233A1
公开(公告)日：2009-07-30
申请号：US12043747
申请日：2008-03-06
申请人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
发明人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
IPC分类号： G06F9/318
CPC分类号： G06F9/3861 , G06F9/30189 , G06F9/383 , G06F9/3842
摘要： A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.
摘要翻译：一种用于避免投机访问中检查停止的方法和处理器。执行单元，例如加载/存储单元，可以被耦合到被配置为存储指令的队列。耦合到执行单元的寄存器可被配置为存储对应于物理存储器中的地址的值。当处理器以实模式运行时，执行单元可以检索存储在寄存器中的值。在执行单元从队列接收诸如推测性加载指令的推测性指令之后，可以确定推测指令的地址是否在检索值以下。如果推测指令的地址处于或低于该值，则执行单元可以安全地推测性地执行该指令，同时避免检查停止，因为已知存在于该物理存储器中的所有地址或低于该值的地址。

8. 发明授权

US07370177B2 Mechanism for avoiding check stops in speculative accesses while operating in real mode 失效
标题翻译：在实模式下运行时避免检测停止的机制
公开(公告)号：US07370177B2
公开(公告)日：2008-05-06
申请号：US10424527
申请日：2003-04-25
申请人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
发明人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/30189 , G06F9/383 , G06F9/3842
摘要： A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.
摘要翻译：一种用于避免投机访问中检查停止的方法和处理器。执行单元，例如加载/存储单元，可以被耦合到被配置为存储指令的队列。耦合到执行单元的寄存器可被配置为存储对应于物理存储器中的地址的值。当处理器以实模式运行时，执行单元可以检索存储在寄存器中的值。在执行单元从队列接收诸如推测性加载指令的推测性指令之后，可以确定推测指令的地址是否在检索值以下。如果推测指令的地址处于或低于该值，则执行单元可以安全地推测性地执行该指令，同时避免检查停止，因为已知存在于该物理存储器中的所有地址或低于该值的地址。

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