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1. 发明授权

US5495590A Checkpoint synchronization with instruction overlap enabled 失效
标题翻译：检查点同步与启用指令重叠
公开(公告)号：US5495590A
公开(公告)日：1996-02-27
申请号：US480107
申请日：1995-06-07
申请人： Steven T. Comfort , Clifford O. Hayden , John S. Liptay , Susan B. Stillman , Charles F. Webb
发明人： Steven T. Comfort , Clifford O. Hayden , John S. Liptay , Susan B. Stillman , Charles F. Webb
IPC分类号： G06F9/38 , G06F11/14
CPC分类号： G06F9/3863 , G06F11/1407
摘要： An instruction processing system and method which utilizes instruction completion to isolate errors, including those in the post-completion processing of operand stores, to an interval between checkpoints, while allowing the processing of checkpointing instructions to be overlapped with that of other instructions. Checkpoints are established before and after such instructions, and all processing (including that of operand stores) from before a checkpoint must be done prior to allowing instruction completion to move beyond the checkpoint. Nevertheless, instructions from beyond a checkpoint are allowed to be processed up to the point of completion while waiting for the checkpoint to be cleared. The point at which instructions must wait on a prior checkpoint is thus moved to the final phase of instruction processing (instruction completion), at significant performance advantage over a conventional implementation in which this waiting is done at instruction fetch, decode, or execution time.
摘要翻译：一种指令处理系统和方法，其使用指令完成将包括操作数存储器的后完成处理中的错误的错误隔离到检查点之间的间隔，同时允许检查点指令的处理与其他指令的处理重叠。在这些指令之前和之后建立检查点，并且必须在允许指令完成超出检查点之前完成检查点之前的所有处理（包括操作数存储的处理）。然而，在等待检查点被清除之前，允许超出检查点的指令被处理到完成点。因此，相对于在指令获取，解码或执行时间完成这种等待的常规实现，指令必须在先前检查点上等待的点被移动到指令处理（指令完成）的最后阶段。

2. 发明授权

US5495587A Method for processing checkpoint instructions to allow concurrent execution of overlapping instructions 失效
标题翻译：用于处理检查点指令以允许并发执行重叠指令的方法
公开(公告)号：US5495587A
公开(公告)日：1996-02-27
申请号：US263497
申请日：1994-06-21
申请人： Steven T. Comfort , Clifford O. Hayden , John S. Liptay , Susan B. Stillman , Charles F. Webb
发明人： Steven T. Comfort , Clifford O. Hayden , John S. Liptay , Susan B. Stillman , Charles F. Webb
IPC分类号： G06F9/38 , G06F11/14
CPC分类号： G06F9/3863 , G06F11/1407
摘要： An instruction processing system and method which utilizes instruction completion to isolate errors, including those in the post-completion processing of operand stores, to an interval between checkpoints, while allowing the processing of checkpointing instructions to be overlapped with that of other instructions. Checkpoints are established before and after such instructions, and all processing (including that of operand stores) from before a checkpoint must be done prior to allowing instruction completion to move beyond the checkpoint. Nevertheless, instructions from beyond a checkpoint are allowed to be processed up to the point of completion while waiting for the checkpoint to be cleared. The point at which instructions must wait on a prior checkpoint is thus moved to the final phase of instruction processing (instruction completion), at significant performance advantage over a conventional implementation in which this waiting is done at instruction fetch, decode, or execution time.
摘要翻译：一种指令处理系统和方法，其使用指令完成将包括操作数存储器的后完成处理中的错误的错误隔离到检查点之间的间隔，同时允许检查点指令的处理与其他指令的处理重叠。在这些指令之前和之后建立检查点，并且必须在允许指令完成超出检查点之前完成检查点之前的所有处理（包括操作数存储的处理）。然而，在等待检查点被清除之前，允许超出检查点的指令被处理到完成点。因此，相对于在指令获取，解码或执行时间完成这种等待的常规实现，指令必须在先前检查点上等待的点被移动到指令处理（指令完成）的最后阶段。

3. 发明授权

US5386560A Execution of page data transfer by PT processors and issuing of split start and test instructions by CPUs coordinated by queued tokens 失效
标题翻译：由PT处理器执行页面数据传输，并由排队令牌协调的CPU发出拆分启动和测试指令
公开(公告)号：US5386560A
公开(公告)日：1995-01-31
申请号：US704559
申请日：1991-05-23
申请人： Donald W. McCauley , Richard J. Schmalz , Ronald M. Smith, Sr. , Susan B. Stillman
发明人： Donald W. McCauley , Richard J. Schmalz , Ronald M. Smith, Sr. , Susan B. Stillman
IPC分类号： G06F13/42 , G06F12/02 , G06F13/16 , G06F15/17 , G06F13/14
CPC分类号： G06F15/17 , G06F13/1642
摘要： Asynchronously transfers blocks of data (called pages) between two different electronic media of a data processing system. The different media may be a system main storage and a system expanded storage or a non-volatile external type of storage, either of which use different addressing than the main storage. All of these storages may be made of DRAM or SRAM technology with battery backup when necessary. The invention splits the involvement of a program requesting a page transfer into a pair of instructions per page transfer executing on one or more central processors. The first instruction of a pair starts another processor that controls the asynchronous page transfer, and the second instruction of the pair enables the communication of the end of the page transfer to the program. Neither instruction in the pair interrupts the program for the page transfer. A processor executing the starting instruction is immediately free to execute any other available instructions. Although both instructions in a pair may be executed by one processor, the pair may be executed by separate processors. And the execution of other instructions may overlap the page transfer between the execution of the pair.
摘要翻译：在数据处理系统的两个不同电子介质之间异步传输数据块（称为页）。不同的媒体可以是系统主存储和系统扩展存储或非易失性外部类型的存储，其中任何一种使用与主存储不同的寻址。所有这些存储器可以由DRAM或SRAM技术制成，并在需要时进行电池备份。本发明将请求页面传送的程序的参与划分为在一个或多个中央处理器上执行的每页传送的一对指令。一对的第一条指令启动另一个控制异步页面传输的处理器，该对的第二条指令使页面传送结束的通信能够与程序通信。配对中的任一条指令都不会中断程序进行页面传送。执行启动指令的处理器可以随时执行任何其他可用的指令。虽然一对处理器可以执行一对指令，但该对可以由单独的处理器执行。并且其他指令的执行可能在对的执行之间与页面传送重叠。

4. 发明授权

US5345567A System and method for modifying program status word system mask, system access key, and address space code with overlap enabled 失效
标题翻译：用于修改程序状态字系统掩码，系统访问密钥和启用重叠的地址空间代码的系统和方法
公开(公告)号：US5345567A
公开(公告)日：1994-09-06
申请号：US712285
申请日：1991-06-10
申请人： Clifford O. Hayden , David R. Snyder , Susan B. Stillman , Charles F. Webb
发明人： Clifford O. Hayden , David R. Snyder , Susan B. Stillman , Charles F. Webb
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/312
CPC分类号： G06F9/30094 , G06F9/30101 , G06F9/3842
摘要： A system and method for modifying program status words (PSW) with overlap enabled. According to the present invention, an instruction which modifies a PSW system mask, access key, or address space code is executed with overlap enabled. This instruction generates a new PSW. The new PSW is pushed into a queue. Once the instruction is complete, the new PSW becomes an architected PSW. If the instruction does not complete, then the new PSW is discarded. Once the new PSW is pushed into the queue, subsequent instructions may execute using the new PSW. Thus, instructions which modify the PSW system mask, access key, and address space code may execute with overlap enabled.
摘要翻译：一种用于修改启用重叠的程序状态字（PSW）的系统和方法。根据本发明，在重叠使能的情况下执行修改PSW系统掩码，访问密钥或地址空间代码的指令。该指令生成新的PSW。新的PSW被推入队列。指令完成后，新的PSW将成为一个架构化的PSW。如果指令未完成，则新的PSW被丢弃。一旦新的PSW被推入队列，后续指令可以使用新的PSW执行。因此，修改PSW系统掩码，访问密钥和地址空间代码的指令可以在启用重叠的情况下执行。

5. 发明授权

US5269017A Type 1, 2 and 3 retry and checkpointing 失效
标题翻译：类型1，2和3重试和检查点
公开(公告)号：US5269017A
公开(公告)日：1993-12-07
申请号：US751906
申请日：1991-08-29
申请人： Clifford O. Hayden , Robert J. Hurban , Donald W. McCauley , John S. Murdock, Jr. , Susan B. Stillman
发明人： Clifford O. Hayden , Robert J. Hurban , Donald W. McCauley , John S. Murdock, Jr. , Susan B. Stillman
IPC分类号： G06F9/38 , G06F11/14 , G06F9/46
CPC分类号： G06F9/3863 , G06F11/1407 , G06F9/384
摘要： An improved error recovery system in which all operations which the Central Processor performs are categorized into one of a plurality of recovery types. The determination of category is made based on which architected and machine dependent facilities they manipulate and the manner in which the facilities are manipulated. This classification of instructions into types allows for the amount of checkpoint data to be minimized while allowing recovery to be generalized into broad algorithms instead of handling each operation independently. Furthermore, by applying this classification technique to various phases of execution (recovery windows) of instructions which modify system facilities before they complete, these instructions can also be retried with a minimum of hardware and algorithms.

6. 发明授权

US5293613A Recovery control register 失效
标题翻译：恢复控制寄存器
公开(公告)号：US5293613A
公开(公告)日：1994-03-08
申请号：US751461
申请日：1991-08-29
申请人： Clifford O. Hayden , Robert J. Hurban , Susan B. Stillman
发明人： Clifford O. Hayden , Robert J. Hurban , Susan B. Stillman
IPC分类号： G06F9/38 , G06F11/14 , G06F15/00
CPC分类号： G06F11/141 , G06F9/3863
摘要： A Recovery Control Register is embodied as two multi-bit registers; a staged register and an immediate register. The immediate register contains the information which is read by the CP microcode and used during recovery. The staged register is a platform where a footprint can be assembled by the CP microcode before the retry checkpoint is changed. The CP microcode can operate on either register through the use of "SET", "AND" and "OR" functions. The choice of these operators as well as the decision to separate the registers into bit ranges provides the microcode with maximum flexibility when setting up new checkpoint values. When a recovery algorithm requires that the recovery footprint change immediately, microcode operates on the immediate register. If, however, the recovery footprint needs to be synchronized with the event which requires the change, for example a store being released, the microcode puts the appropriate footprint into the staged register and issues a release signal to the completion/interrupt logic within the CP. When the release is processed and broadcast as a Completion Report a variable number of cycles later, the checkpoint is advanced and the immediate register is updated in the same cycle, thereby allowing for a crisp transition from one recovery window to the next.
摘要翻译：恢复控制寄存器被实现为两个多位寄存器; 分期登记册和立即登记册。立即注册包含由CP微代码读取并在恢复期间使用的信息。分级寄存器是一个平台，在重试检查点更改之前，脚本可以由CP微代码组合。 CP微代码可以通过使用“SET”，“AND”和“OR”功能在任一寄存器中进行操作。这些操作符的选择以及将寄存器分成位范围的决定在设置新的检查点值时提供了微代码的最大灵活性。当恢复算法要求恢复足迹立即更改时，微代码对立即注册器进行操作。然而，如果恢复足迹需要与需要更改的事件（例如，正在释放的存储）同步，则微代码将适当的占用空间放入分段寄存器，并向CP内的完成/中断逻辑发出释放信号。当释放被处理并作为完成报告广播作为可变数量的周期时，检查点被提前并且即时寄存器在相同的周期中更新，从而允许从一个恢复窗口到下一个恢复窗口的清晰过渡。

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