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1. 发明授权

US5345567A System and method for modifying program status word system mask, system access key, and address space code with overlap enabled 失效
标题翻译：用于修改程序状态字系统掩码，系统访问密钥和启用重叠的地址空间代码的系统和方法
公开(公告)号：US5345567A
公开(公告)日：1994-09-06
申请号：US712285
申请日：1991-06-10
申请人： Clifford O. Hayden , David R. Snyder , Susan B. Stillman , Charles F. Webb
发明人： Clifford O. Hayden , David R. Snyder , Susan B. Stillman , Charles F. Webb
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/312
CPC分类号： G06F9/30094 , G06F9/30101 , G06F9/3842
摘要： A system and method for modifying program status words (PSW) with overlap enabled. According to the present invention, an instruction which modifies a PSW system mask, access key, or address space code is executed with overlap enabled. This instruction generates a new PSW. The new PSW is pushed into a queue. Once the instruction is complete, the new PSW becomes an architected PSW. If the instruction does not complete, then the new PSW is discarded. Once the new PSW is pushed into the queue, subsequent instructions may execute using the new PSW. Thus, instructions which modify the PSW system mask, access key, and address space code may execute with overlap enabled.
摘要翻译：一种用于修改启用重叠的程序状态字（PSW）的系统和方法。根据本发明，在重叠使能的情况下执行修改PSW系统掩码，访问密钥或地址空间代码的指令。该指令生成新的PSW。新的PSW被推入队列。指令完成后，新的PSW将成为一个架构化的PSW。如果指令未完成，则新的PSW被丢弃。一旦新的PSW被推入队列，后续指令可以使用新的PSW执行。因此，修改PSW系统掩码，访问密钥和地址空间代码的指令可以在启用重叠的情况下执行。

2. 发明授权

US5495587A Method for processing checkpoint instructions to allow concurrent execution of overlapping instructions 失效
标题翻译：用于处理检查点指令以允许并发执行重叠指令的方法
公开(公告)号：US5495587A
公开(公告)日：1996-02-27
申请号：US263497
申请日：1994-06-21
申请人： Steven T. Comfort , Clifford O. Hayden , John S. Liptay , Susan B. Stillman , Charles F. Webb
发明人： Steven T. Comfort , Clifford O. Hayden , John S. Liptay , Susan B. Stillman , Charles F. Webb
IPC分类号： G06F9/38 , G06F11/14
CPC分类号： G06F9/3863 , G06F11/1407
摘要： An instruction processing system and method which utilizes instruction completion to isolate errors, including those in the post-completion processing of operand stores, to an interval between checkpoints, while allowing the processing of checkpointing instructions to be overlapped with that of other instructions. Checkpoints are established before and after such instructions, and all processing (including that of operand stores) from before a checkpoint must be done prior to allowing instruction completion to move beyond the checkpoint. Nevertheless, instructions from beyond a checkpoint are allowed to be processed up to the point of completion while waiting for the checkpoint to be cleared. The point at which instructions must wait on a prior checkpoint is thus moved to the final phase of instruction processing (instruction completion), at significant performance advantage over a conventional implementation in which this waiting is done at instruction fetch, decode, or execution time.
摘要翻译：一种指令处理系统和方法，其使用指令完成将包括操作数存储器的后完成处理中的错误的错误隔离到检查点之间的间隔，同时允许检查点指令的处理与其他指令的处理重叠。在这些指令之前和之后建立检查点，并且必须在允许指令完成超出检查点之前完成检查点之前的所有处理（包括操作数存储的处理）。然而，在等待检查点被清除之前，允许超出检查点的指令被处理到完成点。因此，相对于在指令获取，解码或执行时间完成这种等待的常规实现，指令必须在先前检查点上等待的点被移动到指令处理（指令完成）的最后阶段。

3. 发明授权

US5495590A Checkpoint synchronization with instruction overlap enabled 失效
标题翻译：检查点同步与启用指令重叠
公开(公告)号：US5495590A
公开(公告)日：1996-02-27
申请号：US480107
申请日：1995-06-07
申请人： Steven T. Comfort , Clifford O. Hayden , John S. Liptay , Susan B. Stillman , Charles F. Webb
发明人： Steven T. Comfort , Clifford O. Hayden , John S. Liptay , Susan B. Stillman , Charles F. Webb
IPC分类号： G06F9/38 , G06F11/14
CPC分类号： G06F9/3863 , G06F11/1407
摘要： An instruction processing system and method which utilizes instruction completion to isolate errors, including those in the post-completion processing of operand stores, to an interval between checkpoints, while allowing the processing of checkpointing instructions to be overlapped with that of other instructions. Checkpoints are established before and after such instructions, and all processing (including that of operand stores) from before a checkpoint must be done prior to allowing instruction completion to move beyond the checkpoint. Nevertheless, instructions from beyond a checkpoint are allowed to be processed up to the point of completion while waiting for the checkpoint to be cleared. The point at which instructions must wait on a prior checkpoint is thus moved to the final phase of instruction processing (instruction completion), at significant performance advantage over a conventional implementation in which this waiting is done at instruction fetch, decode, or execution time.
摘要翻译：一种指令处理系统和方法，其使用指令完成将包括操作数存储器的后完成处理中的错误的错误隔离到检查点之间的间隔，同时允许检查点指令的处理与其他指令的处理重叠。在这些指令之前和之后建立检查点，并且必须在允许指令完成超出检查点之前完成检查点之前的所有处理（包括操作数存储的处理）。然而，在等待检查点被清除之前，允许超出检查点的指令被处理到完成点。因此，相对于在指令获取，解码或执行时间完成这种等待的常规实现，指令必须在先前检查点上等待的点被移动到指令处理（指令完成）的最后阶段。

4. 发明授权

US10338923B2 Branch prediction path wrong guess instruction 有权
公开(公告)号：US10338923B2
公开(公告)日：2019-07-02
申请号：US12435631
申请日：2009-05-05
申请人： Philip G. Emma , Allan M. Hartstein , Keith N. Langston , Brian R. Prasky , Thomas R. Puzak , Charles F. Webb
发明人： Philip G. Emma , Allan M. Hartstein , Keith N. Langston , Brian R. Prasky , Thomas R. Puzak , Charles F. Webb
IPC分类号： G06F9/30 , G06F9/38 , G06F12/0862 , G06F8/41
摘要： A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address.

5. 发明授权

US08621180B2 Dynamic address translation with translation table entry format control for identifying format of the translation table entry 有权
标题翻译：动态地址转换与翻译表格格式控制，用于识别翻译表格的格式
公开(公告)号：US08621180B2
公开(公告)日：2013-12-31
申请号：US13336106
申请日：2011-12-23
申请人： Dan F Greiner , Lisa C Heller , Damian L Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
发明人： Dan F Greiner , Lisa C Heller , Damian L Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/1009 , G06F12/1027
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.
摘要翻译：提供的是增强的动态地址转换设施。在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。虚拟地址的索引部分用于引用转换表中的条目。如果启用了转换表条目中包含的格式控制字段，则表项包含大小至少为1M字节的大块数据的帧地址。然后将帧地址与虚拟地址的偏移部分组合以形成主存储器或存储器中的小4K字节数据块的转换地址。

6. 发明授权

US08112174B2 Processor, method and computer program product for fast selective invalidation of translation lookaside buffer 有权
标题翻译：处理器，方法和计算机程序产品，用于快速选择性地无效翻译后备缓冲区
公开(公告)号：US08112174B2
公开(公告)日：2012-02-07
申请号：US12036398
申请日：2008-02-25
申请人： Jonathan T. Hsieh , Chung-Lung Kevin Shum , Charles F. Webb
发明人： Jonathan T. Hsieh , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each comparator associated with a respective output of each TLB set output for each TLB port, wherein each of the comparators is adapted for identifying mappings for invalidation; and logic for invalidating each identified mapping. A method and a computer program product are provided.
摘要翻译：一种处理器，包括适于使至少一个逻辑地址映射至少一个绝对地址无效的微体系结构，包括：至少一个翻译后备缓冲器（TLB）及其多个副本; 独立索引TLB每份副本的逻辑; 多个比较器，每个比较器与每个TLB端口的每个TLB组输出的相应输出相关联，其中每个比较器适于识别无效化的映射; 以及使每个识别的映射无效的逻辑。提供了一种方法和计算机程序产品。

7. 发明申请

US20110320774A1 OPERAND FETCHING CONTROL AS A FUNCTION OF BRANCH CONFIDENCE 有权
标题翻译：操作控制作为分支机构的功能
公开(公告)号：US20110320774A1
公开(公告)日：2011-12-29
申请号：US12822379
申请日：2010-06-24
申请人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
发明人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
IPC分类号： G06F9/38
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3806 , G06F9/3844 , G06F9/3857
摘要： A system for data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.
摘要翻译：一种用于数据操作数取出控制的系统包括一计算机处理器，该计算机处理器包括用于确定存储器访问操作的控制控制单元被配置为执行方法。该方法包括：计算流水线中每个指令的求和权重值，求和作为分支不确定度的函数计算的求和权重值以及相对于流水线中的其他指令，指令驻留在流水线中的挂起。该方法还包括将尝试访问系统存储器的所选择的指令的求和权重值映射到存储器访问控制，每个存储器访问控制指定处理数据获取操作的方式。该方法还包括基于映射执行针对所选择的指令的存储器访问操作。

8. 发明授权

US07966474B2 System, method and computer program product for translating storage elements 有权
标题翻译：用于翻译存储元件的系统，方法和计算机程序产品
公开(公告)号：US07966474B2
公开(公告)日：2011-06-21
申请号：US12036520
申请日：2008-02-25
申请人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
IPC分类号： G06F9/26
CPC分类号： G06F9/3017 , G06F9/30018 , G06F9/30101 , G06F9/355
摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.
摘要翻译：一种用于计算机系统中的翻译的系统，方法和计算机程序产品。该系统包括包含地址转换表的基地址的通用寄存器。该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

9. 发明申请

US20100287358A1 Branch Prediction Path Instruction 审中-公开
标题翻译：分支预测路径指令
公开(公告)号：US20100287358A1
公开(公告)日：2010-11-11
申请号：US12435631
申请日：2009-05-05
申请人： Philip G. Emma , Allan M. Hartstein , Keith N. Langston , Brian R. Prasky , Thomas R. Puzak , Charles F. Webb
发明人： Philip G. Emma , Allan M. Hartstein , Keith N. Langston , Brian R. Prasky , Thomas R. Puzak , Charles F. Webb
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30047 , G06F8/4442 , G06F9/3005 , G06F9/30054 , G06F9/30058 , G06F9/30076 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/383 , G06F9/3842 , G06F9/3844 , G06F9/3846 , G06F9/3848 , G06F12/0862 , G06F2212/6028
摘要： A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address.
摘要翻译：一种分支预测方法，所述方法包括：接收具有分支错误猜测指令地址的分支错误猜测指令和包括操作码和分支目标地址的数据，确定分支错误猜测指令是否由分支预测机制预测，发送分支对执行单元的错误猜测指令响应于确定分支错误猜测指令由分支预测机制预测，以及在分支目标地址处的接收和解码指令。

10. 发明申请

US20090217264A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PROVIDING FILTERING OF GUEST2 QUIESCE REQUESTS 失效
标题翻译：方法，系统和计算机程序产品，用于提供GUEST2 QUIESCE要求的过滤
公开(公告)号：US20090217264A1
公开(公告)日：2009-08-27
申请号：US12037887
申请日：2008-02-26
申请人： Lisa C. Heller , Damian L. Osisek , Charles F. Webb
发明人： Lisa C. Heller , Damian L. Osisek , Charles F. Webb
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F2009/45566
摘要： A method, system and computer program product for providing filtering of level two guest (G2) quiesce requests. The method includes receiving a G2 quiesce interruption request at a processor currently or previously executing a G2 running under a level two hypervisor in a logical partition. The G2 includes a current zone and G2 virtual machine (VM) identifier. The quiesce interruption request specifies an initiating zone and an initiating G2 VM identifier. It is determined if the G2 quiesce interruption request can be filtered by the processor. The determining is responsive to the current G2 VM identifier, the current zone, the initiating zone and the initiating G2 VM identifier. The G2 quiesce interruption request is filtered at the processor in response to determining that the G2 quiesce interruption request can be filtered. Thus, filtering between G2 virtual machines running in the logical partition is provided.
摘要翻译：一种用于提供二级客户（G2）静默请求过滤的方法，系统和计算机程序产品。该方法包括在当前或先前执行在逻辑分区中的二级虚拟机管理程序下运行的G2的处理器处接收G2停顿中断请求。 G2包括当前区域和G2虚拟机（VM）标识符。静默中断请求指定启动区域和启动G2 VM标识符。确定G2停顿中断请求是否可以被处理器过滤。该确定响应于当前的G2 VM标识符，当前区域，起始区域和起始G2 VM标识符。响应于确定可以过滤G2静默中断请求，在处理器处对G2静默中断请求进行过滤。因此，提供了在逻辑分区中运行的G2虚拟机之间的过滤。

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