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1. 发明授权

US5269017A Type 1, 2 and 3 retry and checkpointing 失效
标题翻译：类型1，2和3重试和检查点
公开(公告)号：US5269017A
公开(公告)日：1993-12-07
申请号：US751906
申请日：1991-08-29
申请人： Clifford O. Hayden , Robert J. Hurban , Donald W. McCauley , John S. Murdock, Jr. , Susan B. Stillman
发明人： Clifford O. Hayden , Robert J. Hurban , Donald W. McCauley , John S. Murdock, Jr. , Susan B. Stillman
IPC分类号： G06F9/38 , G06F11/14 , G06F9/46
CPC分类号： G06F9/3863 , G06F11/1407 , G06F9/384
摘要： An improved error recovery system in which all operations which the Central Processor performs are categorized into one of a plurality of recovery types. The determination of category is made based on which architected and machine dependent facilities they manipulate and the manner in which the facilities are manipulated. This classification of instructions into types allows for the amount of checkpoint data to be minimized while allowing recovery to be generalized into broad algorithms instead of handling each operation independently. Furthermore, by applying this classification technique to various phases of execution (recovery windows) of instructions which modify system facilities before they complete, these instructions can also be retried with a minimum of hardware and algorithms.

2. 发明授权

US5293613A Recovery control register 失效
标题翻译：恢复控制寄存器
公开(公告)号：US5293613A
公开(公告)日：1994-03-08
申请号：US751461
申请日：1991-08-29
申请人： Clifford O. Hayden , Robert J. Hurban , Susan B. Stillman
发明人： Clifford O. Hayden , Robert J. Hurban , Susan B. Stillman
IPC分类号： G06F9/38 , G06F11/14 , G06F15/00
CPC分类号： G06F11/141 , G06F9/3863
摘要： A Recovery Control Register is embodied as two multi-bit registers; a staged register and an immediate register. The immediate register contains the information which is read by the CP microcode and used during recovery. The staged register is a platform where a footprint can be assembled by the CP microcode before the retry checkpoint is changed. The CP microcode can operate on either register through the use of "SET", "AND" and "OR" functions. The choice of these operators as well as the decision to separate the registers into bit ranges provides the microcode with maximum flexibility when setting up new checkpoint values. When a recovery algorithm requires that the recovery footprint change immediately, microcode operates on the immediate register. If, however, the recovery footprint needs to be synchronized with the event which requires the change, for example a store being released, the microcode puts the appropriate footprint into the staged register and issues a release signal to the completion/interrupt logic within the CP. When the release is processed and broadcast as a Completion Report a variable number of cycles later, the checkpoint is advanced and the immediate register is updated in the same cycle, thereby allowing for a crisp transition from one recovery window to the next.
摘要翻译：恢复控制寄存器被实现为两个多位寄存器; 分期登记册和立即登记册。立即注册包含由CP微代码读取并在恢复期间使用的信息。分级寄存器是一个平台，在重试检查点更改之前，脚本可以由CP微代码组合。 CP微代码可以通过使用“SET”，“AND”和“OR”功能在任一寄存器中进行操作。这些操作符的选择以及将寄存器分成位范围的决定在设置新的检查点值时提供了微代码的最大灵活性。当恢复算法要求恢复足迹立即更改时，微代码对立即注册器进行操作。然而，如果恢复足迹需要与需要更改的事件（例如，正在释放的存储）同步，则微代码将适当的占用空间放入分段寄存器，并向CP内的完成/中断逻辑发出释放信号。当释放被处理并作为完成报告广播作为可变数量的周期时，检查点被提前并且即时寄存器在相同的周期中更新，从而允许从一个恢复窗口到下一个恢复窗口的清晰过渡。

3. 发明授权

US4916703A Handling errors in the C bit of a storage key 失效
标题翻译：处理存储密钥的C位中的错误
公开(公告)号：US4916703A
公开(公告)日：1990-04-10
申请号：US276736
申请日：1988-11-28
申请人： Neal T. Christensen , Steven T. Comfort , Robert J. Hurban , Bruce L. McGilvray , Arthur J. Sutton , James R. Urquhart , David R. Willoughby
发明人： Neal T. Christensen , Steven T. Comfort , Robert J. Hurban , Bruce L. McGilvray , Arthur J. Sutton , James R. Urquhart , David R. Willoughby
IPC分类号： G06F11/10 , G06F11/00
CPC分类号： G06F11/00 , G06F11/10
摘要： A method of handling errors in the C bit of a storage key by modifying the INSERT STORAGE KEY (ISK) and the RESET REFERENCE BIT (RRB) instructions. If an error is found in the C bit during the execution of these instructions, microcode is instructed to refresh the C bit. The C bit is interrogated a second time to determine if the refreshed C bit is still in error. If the refreshed C bit is not in error a second time, then the first error was caused by a soft or transient error, and the instruction is continued. If the refreshed C bit is in error a second time then the first and second errors were caused by a permanent error such as a stuck bit, and a system recovery machine check error is generated. The handling of C bit errors is thus done in a dynamic fashion as the instructions are executed.

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