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1. 发明授权

US4521846A Mechanism for accessing multiple virtual address spaces 失效
公开(公告)号：US4521846A
公开(公告)日：1985-06-04
申请号：US236387
申请日：1981-02-20
申请人： Casper A. Scalzi , Richard J. Schmalz
发明人： Casper A. Scalzi , Richard J. Schmalz
IPC分类号： G06F9/46 , G06F12/02 , G06F12/10 , G06F13/00
CPC分类号： G06F12/0292
摘要： The disclosure provides a general purpose register (GR) mask which associates predesignated address spaces with respective GRs assigned to contain a base value for calculating logical addresses within the address spaces. An address space mask register has a plurality of digit positions which receive the respective digit values comprising a particular GR mask. A respective digit position is selected by a base GR address signal provided by a storage address request from a CPU instruction decoder. The particular value of the selected digit in the mask register controls the selection among a plurality of STO registers, which designate a plurality of simultaneously available address spaces. The selected base GR is used in a System/370 B, D or X, B, D type of logical storage address representation. A base GR explicitly contains an intra-address-space base value. The GR mask assigns an implicit inter-address-space designation to the base GR in a simple manner which is handled by conventional address translation hardware. The available address spaces are respectively designated in STO registers by segment table addresses (called STOs). Any number of STO registers (and available address spaces) may be provided up to the radix of each digit in the GR mask. The executing program exists in the address space designated in one of the STO registers. A plurality of storage protect key registers are respectively associated with the STO registers to control the accessing authorized to the executing program within each available address space. The key value may be independently authorized and provided for each available address space. A cross-memory implementation results which enables a compatible extension of the IBM System/370 architecture by permitting the unrestricted use of all S/370 instructions including storage-to-storage (SS) instructions that can access data simultaneously in plural address spaces in non-privileged state.

2. 发明授权

US4355355A Address generating mechanism for multiple virtual spaces 失效
标题翻译：多个虚拟空间的地址生成机制
公开(公告)号：US4355355A
公开(公告)日：1982-10-19
申请号：US131570
申请日：1980-03-19
申请人： Justin R. Butwell , Casper A. Scalzi , Richard J. Schmalz
发明人： Justin R. Butwell , Casper A. Scalzi , Richard J. Schmalz
IPC分类号： G06F9/34 , G06F12/06 , G06F12/10 , G06F12/14 , G06F9/36
CPC分类号： G06F12/1475 , G06F12/0623 , G06F12/1036
摘要： The detailed embodiment associates access registers (AR's) with the general purpose registers (GPR's) in a data processor. The AR's are each loaded with a unique STD (segment table descriptor). The STD comprises a segment table address in main storage and a segment table length field. There are 15 AR's associated respectively with 15 GPR's in a processor to define a subset of up to 15 data address spaces. The STD in an AR is selected for address translation when the associated GPR is selected as a storage operand base register, such as being the GPR selected by the B-field in an IBM System/370 instruction. The invention allows each AR to specify that it does not use the STD in its associated AR to define its data address space, but instead uses the STD in the program address space AR. However, the STD content of an AR is not selected for an address translation if the associated GPR is selected for a purpose other than as a storage operand base register, such as if a GPR is selected as an index (X) register or as a data source or sink register (R) for an instruction. A sixteenth AR may be provided to define and control the executing program address space, which may also contain data.The embodiment obtains authority and other control for access to and use of the content in each address space by also associating an AR Control Vector (ARCV) register with each AR.
摘要翻译：详细实施例将访问寄存器（AR）与通用寄存器（GPR）在数据处理器中相关联。每个AR都加载了一个唯一的STD（段表描述符）。 STD包括主存储器中的段表地址和段表长度字段。在处理器中有15个AR分别与15个GPR相关联，以定义多达15个数据地址空间的子集。当选择相关联的GPR作为存储操作数基址寄存器时，AR中的STD被选择用于地址转换，例如由IBM System / 370指令中的B字段选择的GPR。本发明允许每个AR指定它不使用其关联的AR中的STD来定义其数据地址空间，而是在程序地址空间AR中使用STD。然而，如果相关联的GPR被选择用于除了作为存储操作数的基本寄存器之外的目的，例如如果选择GPR作为索引（X）寄存器或者作为索引（X）寄存器，则不选择AR的STD内容用于地址转换用于指令的数据源或接收寄存器（R）。可以提供第十六AR以定义和控制也可以包含数据的执行程序地址空间。该实施例还通过将AR控制向量（ARCV）寄存器与每个AR相关联来获得对每个地址空间中的内容的访问和使用的权限和其他控制。

3. 发明授权

US5454086A Dynamic program analyzer facility 失效
标题翻译：动态程序分析仪设备
公开(公告)号：US5454086A
公开(公告)日：1995-09-26
申请号：US928937
申请日：1992-08-11
申请人： Alan I. Alpert , Carl E. Clark , Michel H. T. Hack , Casper A. Scalzi , Richard J. Schmalz, deceased , Bhaskar Sinha
发明人： Alan I. Alpert , Carl E. Clark , Michel H. T. Hack , Casper A. Scalzi , Richard J. Schmalz, deceased , Bhaskar Sinha
IPC分类号： G06F11/28 , G06F9/40 , G06F11/36 , G06F9/00 , G06F11/00
CPC分类号： G06F11/3636 , G06F9/4425
摘要： Provides a dynamic execution link between an analyzer program and each hook instruction in a program. Special types of hook instructions are provided for use in a hooked program. The link causes the analyzer program to execute as part of a continuous uninterrupted execution for each hook instruction. The link uses hardware and/or internal code to access a hook control area which provides linkage information needed to invoke the execution of the analyzer program upon completion of the hook instruction and to continue the execution of the hooked program following the completion of the analyzer program. The linkage information includes the entry location into the analyzer program, and also locates the first hook work area (HWA) of a sequence of HWAs, from which an HWA is assigned to each current hook instruction. The assigned HWA stores a return point location in the hooked program at an instruction following the current hook instruction. One or more hooked programs may concurrently use the same analyzer program. As soon as execution by the analyzer program ends for a hook instruction, its assigned HWA is released for use by another hook instruction.
摘要翻译：在分析程序与程序中的每个挂钩指令之间提供动态执行链接。提供特殊类型的挂钩指令用于挂钩程序。该链接使分析程序作为每个挂钩指令的连续不间断执行的一部分执行。该链接使用硬件和/或内部代码访问挂钩控制区域，其提供在完成钩指令时调用分析器程序的执行所需的链接信息，并且在分析器程序完成之后继续执行挂钩程序。链接信息包括进入分析器程序的入口位置，并且还定位HWAs序列的第一挂钩工作区域（HWA），HWA被分配给每个当前挂钩指令。所分配的HWA在当前挂钩指令之后的指令处在挂钩程序中存储返回点位置。一个或多个挂钩程序可以同时使用相同的分析程序。一旦分析程序的执行结束为一个挂接指令，其分配的HWA被释放供另一个钩子指令使用。

4. 发明授权

US5237668A Process using virtual addressing in a non-privileged instruction to control the copying of a page of data in or between multiple media 失效
标题翻译：在非特权指令中使用虚拟寻址来控制数据在多媒体之间或之间复制的过程
公开(公告)号：US5237668A
公开(公告)日：1993-08-17
申请号：US424797
申请日：1989-10-20
申请人： Geoffrey O. Blandy , David B. Emmes , Ronald F. Hill , David B. Lindquist , Kenneth E. Plambeck , Casper A. Scalzi , Richard J. Schmalz
发明人： Geoffrey O. Blandy , David B. Emmes , Ronald F. Hill , David B. Lindquist , Kenneth E. Plambeck , Casper A. Scalzi , Richard J. Schmalz
IPC分类号： G06F12/10 , G06F12/14
CPC分类号： G06F12/10 , G06F12/145
摘要： A single non-privileged instruction copies a page of data from a source virtual address in an electronic medium to a destination virtual address in the same or in a different electronic storage medium, and without the intervention of any supervisory program when each medium and the virtual addresses are previously determined. The instruction is not required to specify which medium it will use, does not require its user to know what backing medium it will access, does not require main storage (MS) to be its backing medium, and allows different types of physical addressing to be used by different media. The instruction can lock any page for use in a multi-processor (MP). No physical direction of data movement is provided within the non-privileged machine instruction, which only designates virtual direction of movement. The separation of virtual direction from physical direction is done by avoiding instruction control over selection of electronic media. The non-privileged instruction can nevertheless express a preference for obtaining a copy of the destination page in an electronic medium in which the content of the page can be processed by further instructions. Also, the instruction can cause invocation of a privileged control program to avoid the need for a following condition code test instruction. A privileged instruction is also provided to wait for the completion of the unprivileged instruction and to invalidate a non-MS medium page whether it is unlocked or locked, either correctly or incorrectly.

5. 发明授权

US5095420A Method and system for performing virtual address range mapping in a virtual storage data processing system 失效
标题翻译：在虚拟存储数据处理系统中执行虚拟地址范围映射的方法和系统
公开(公告)号：US5095420A
公开(公告)日：1992-03-10
申请号：US274062
申请日：1988-11-21
申请人： Catherine K. Eilert , Donald H. Gibson , Kenneth G. Rubsam , Casper A. Scalzi , Richard J. Schmalz , Eugene S. Schulze
发明人： Catherine K. Eilert , Donald H. Gibson , Kenneth G. Rubsam , Casper A. Scalzi , Richard J. Schmalz , Eugene S. Schulze
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/109 , G06F12/08
摘要： A linear data set is mapped to one or more non-main storage virtual data spaces. Portions of this data space are then selectively mapped to a "window" in an address space in which an application is executing, and changes made in this "window" are temporarily saved in the data space. After completion of processing, the application may permanently save changed data from the data space to the linear data set.The technique for mapping the data space to the address space may be used to map between two address spaces, and may be extended to encompass third and subsequent spaces, so that a reference to a mapped address in the first space will ultimately be interpreted as a reference to an address in the last mapped space.

6. 发明授权

US5008811A Control mechanism for zero-origin data spaces 失效
标题翻译：零原始数据空间的控制机制
公开(公告)号：US5008811A
公开(公告)日：1991-04-16
申请号：US154688
申请日：1988-02-10
申请人： Casper A. Scalzi , Richard J. Schmalz
发明人： Casper A. Scalzi , Richard J. Schmalz
IPC分类号： G06F12/08 , G06F12/10 , G06F12/14
CPC分类号： G06F12/1475 , G06F12/1036
摘要： Within a data processing system, a control mechanism for supporting a data space without common segments in addition to traditional address spaces containing common segments. Logic for eliminating duplication of lookaside table entries for virtual addresses within shared segments, but not for identical virtual addresses within data address spaces is provided, as well as for overriding low address protection for store operations into data spaces. Thus, the entire virtual addressing range is available to programs wishing to use such data spaces for data isolation and data sharing.

7. 发明授权

US5220669A Linkage mechanism for program isolation 失效
标题翻译：程序隔离的联动机制
公开(公告)号：US5220669A
公开(公告)日：1993-06-15
申请号：US732936
申请日：1991-07-19
申请人： Richard I. Baum , Terry L. Borden , Carol E. Clark , Alan G. Ganek , James Lum , Michael G. Mall , Casper A. Scalzi , Richard J. Schmalz
发明人： Richard I. Baum , Terry L. Borden , Carol E. Clark , Alan G. Ganek , James Lum , Michael G. Mall , Casper A. Scalzi , Richard J. Schmalz
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/46
CPC分类号： G06F9/30054 , G06F9/30076 , G06F9/3851 , G06F9/468
摘要： A computer system has general purpose registers, control registers and access registers for containing information to allow address space capability. A linkage stack uses protected address space to store state information during program call and program return operations. The linkage stack contains information relating to state entries for the saved information and header and trailer entries to point to other linkage stack sections. A control register contains the pointer to the current linkage stack entry and is changed as the program call or return moves through the stack.
摘要翻译：计算机系统具有通用寄存器，控制寄存器和访问寄存器，用于包含允许地址空间能力的信息。链接堆栈在程序调用和程序返回操作期间使用受保护的地址空间来存储状态信息。链接堆栈包含与保存的信息的状态条目相关的信息，以及指向其他链接堆栈部分的报头和尾部条目。控制寄存器包含指向当前链接堆栈条目的指针，并在程序调用或返回移动通过堆栈时更改。

8. 发明授权

US4979098A Multiple address space token designation, protection controls, designation translation and lookaside 失效
标题翻译：多地址空间令牌指定，保护控制，指定翻译和后备
公开(公告)号：US4979098A
公开(公告)日：1990-12-18
申请号：US535248
申请日：1990-06-08
申请人： Richard I. Baum , Terry L. Borden , Justin R. Butwell , Carl E. Clark , Alan G. Ganek , James Lum , Michael G. Mall , Kenneth E. Plambeck , Casper A. Scalzi , Richard J. Schmalz , Ronald M. Smith , Julian Thomas
发明人： Richard I. Baum , Terry L. Borden , Justin R. Butwell , Carl E. Clark , Alan G. Ganek , James Lum , Michael G. Mall , Kenneth E. Plambeck , Casper A. Scalzi , Richard J. Schmalz , Ronald M. Smith , Julian Thomas
IPC分类号： G06F9/46 , G06F12/02 , G06F12/10 , G06F12/14
CPC分类号： G06F9/468 , G06F12/0292 , G06F12/1036 , G06F12/1483
摘要： A method and apparatus is provided to translate the contents of access registers into information for use in performing addressing functions for multiple virtual address spaces. The access registers represent the full addressing capability of the system but do not directly contain the addressing information. The system has a plurality of general purpose registers, a plurality of access registers associated with the general registers, an access list having access list entries which is addressed by the contents of the access register, memory storage for holding address space number second table entries (ASTE), where the contents of the access list entry locate the ASTE and where the ASTE contains the addressing information needed to translate a virtual address when combined with the contents of a general purpose register. Access register translation (ART) consists of the process of determining addressing information by using the access list entry and the ASTE. The results of the ART process are stored in an ART lookaside buffer (ALB) which stores the results of ART while valid for later use.
摘要翻译：提供了一种方法和装置，用于将访问寄存器的内容转换为用于执行多个虚拟地址空间的寻址功能的信息。访问寄存器表示系统的完整寻址能力，但不直接包含寻址信息。该系统具有多个通用寄存器，与通用寄存器相关联的多个访问寄存器，具有由访问寄存器的内容寻址的访问列表条目的访问列表，用于保存地址空间数第二表条目的存储器存储 ASTE），其中访问列表条目的内容定位ASTE，并且ASTE包含当与通用寄存器的内容组合时将虚拟地址翻译所需的寻址信息。访问注册翻译（ART）包括通过使用访问列表条目和ASTE来确定寻址信息的过程。 ART处理的结果存储在ART后视缓冲器（ALB）中，其存储ART的结果，有效期以后使用。

9. 发明授权

US5461721A System for transferring data between I/O devices and main or expanded storage under dynamic control of independent indirect address words (IDAWs) 失效
标题翻译：用于在独立间接地址字（IDAW）的动态控制下在I / O设备与主或扩展存储之间传输数据的系统
公开(公告)号：US5461721A
公开(公告)日：1995-10-24
申请号：US46679
申请日：1993-04-14
申请人： Roger L. Cormier , Robert J. Dugan , Kenneth J. Fredericks , Peter H. Gum , Moon J. Kim , Allen H. Preston , Richard J. Schmalz, deceased , Charles F. Webb , Leslie W. Wyman
发明人： Roger L. Cormier , Robert J. Dugan , Kenneth J. Fredericks , Peter H. Gum , Moon J. Kim , Allen H. Preston , Richard J. Schmalz, deceased , Charles F. Webb , Leslie W. Wyman
IPC分类号： G06F12/08 , G06F12/10 , G06F13/12
CPC分类号： G06F13/122 , G06F12/08 , G06F12/10
摘要： Enables an I/O channel program to use IDAWs (indirect data address words) to control data transfers from/to an I/O (input/output) device to/from either or both of ES (expanded storage) and/or system MS (main storage), in which data moved to/from ES does not move through MS. ES and MS are plural electronic storage media in a data processing system, and the I/O device is any I/O device selectable by the system. Intermixing of data transfers between ES and MS may be controlled by a single IDAW list accessed by a channel control word (CCW) in a channel program in a data transfer direction indicated in the CCW without any channel mode change.
摘要翻译：启用I / O通道程序以使用IDAW（间接数据地址字）来控制从I / O（输入/输出）设备到/从ES（扩展存储）和/或系统MS之一或两者的数据传输（主存储），其中移动到/从ES的数据不通过MS移动。 ES和MS是数据处理系统中的多个电子存储介质，I / O设备是可由系统选择的任何I / O设备。在ES和MS之间的数据传输的混合可以由在CCW中指示的数据传送方向上的信道程序中由信道控制字（CCW）访问的单个IDAW列表来控制，而没有任何信道模式改变。

10. 发明授权

US5386560A Execution of page data transfer by PT processors and issuing of split start and test instructions by CPUs coordinated by queued tokens 失效
标题翻译：由PT处理器执行页面数据传输，并由排队令牌协调的CPU发出拆分启动和测试指令
公开(公告)号：US5386560A
公开(公告)日：1995-01-31
申请号：US704559
申请日：1991-05-23
申请人： Donald W. McCauley , Richard J. Schmalz , Ronald M. Smith, Sr. , Susan B. Stillman
发明人： Donald W. McCauley , Richard J. Schmalz , Ronald M. Smith, Sr. , Susan B. Stillman
IPC分类号： G06F13/42 , G06F12/02 , G06F13/16 , G06F15/17 , G06F13/14
CPC分类号： G06F15/17 , G06F13/1642
摘要： Asynchronously transfers blocks of data (called pages) between two different electronic media of a data processing system. The different media may be a system main storage and a system expanded storage or a non-volatile external type of storage, either of which use different addressing than the main storage. All of these storages may be made of DRAM or SRAM technology with battery backup when necessary. The invention splits the involvement of a program requesting a page transfer into a pair of instructions per page transfer executing on one or more central processors. The first instruction of a pair starts another processor that controls the asynchronous page transfer, and the second instruction of the pair enables the communication of the end of the page transfer to the program. Neither instruction in the pair interrupts the program for the page transfer. A processor executing the starting instruction is immediately free to execute any other available instructions. Although both instructions in a pair may be executed by one processor, the pair may be executed by separate processors. And the execution of other instructions may overlap the page transfer between the execution of the pair.
摘要翻译：在数据处理系统的两个不同电子介质之间异步传输数据块（称为页）。不同的媒体可以是系统主存储和系统扩展存储或非易失性外部类型的存储，其中任何一种使用与主存储不同的寻址。所有这些存储器可以由DRAM或SRAM技术制成，并在需要时进行电池备份。本发明将请求页面传送的程序的参与划分为在一个或多个中央处理器上执行的每页传送的一对指令。一对的第一条指令启动另一个控制异步页面传输的处理器，该对的第二条指令使页面传送结束的通信能够与程序通信。配对中的任一条指令都不会中断程序进行页面传送。执行启动指令的处理器可以随时执行任何其他可用的指令。虽然一对处理器可以执行一对指令，但该对可以由单独的处理器执行。并且其他指令的执行可能在对的执行之间与页面传送重叠。

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