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1. 发明授权

US07772067B2 Methods of forming phase-changeable memory devices using growth-enhancing and growth-inhibiting layers for phase-changeable materials 失效
标题翻译：使用用于相变材料的生长增强和生长抑制层形成相变存储器件的方法
公开(公告)号：US07772067B2
公开(公告)日：2010-08-10
申请号：US12039370
申请日：2008-02-28
申请人： Jinil Lee , Suk Ho Joo , Dohyung Kim , Hyunjun Sim , Hyeyoung Park , Sunglae Cho , Dong-Hyun Im
发明人： Jinil Lee , Suk Ho Joo , Dohyung Kim , Hyunjun Sim , Hyeyoung Park , Sunglae Cho , Dong-Hyun Im
IPC分类号： H01L21/336
CPC分类号： H01L45/144 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1616 , H01L45/1683
摘要： Methods of forming phase-changeable memory devices include techniques to inhibit void formation in phase-changeable materials in order to increase device reliability. These techniques to inhibit void formation use an electrically insulating growth-inhibiting layer to guide the formation of a phase-changeable material region within a memory cell (e.g., PRAM cell). In particular, methods of forming an integrated circuit memory device include forming an interlayer insulating layer having an opening therein, on a substrate, and then lining sidewalls of the opening with a seed layer (i.e., growth-enhancing layer) that supports growth of a phase-changeable material thereon. An electrically insulating growth-inhibiting layer is then selectively formed on a portion of the interlayer insulating layer surrounding the opening. The formation of the growth-inhibiting layer is followed by a step to selectively grow a phase-changeable material region in the opening, but not on the growth-inhibiting layer.
摘要翻译：形成相变存储器件的方法包括抑制相变材料中的空隙形成的技术，以增加器件的可靠性。抑制空隙形成的这些技术使用电绝缘的生长抑制层来引导存储单元（例如，PRAM单元）内的相变材料区域的形成。特别地，形成集成电路存储器件的方法包括在衬底上形成其中具有开口的层间绝缘层，然后用支撑生长的种子层（即生长增强层）来衬套开口的侧壁相变材料。然后在围绕开口的层间绝缘层的一部分上选择性地形成电绝缘的生长抑制层。生长抑制层的形成之后是选择性地生长开口中的相变材料区域，而不是在生长抑制层上生长的步骤。

2. 发明申请

US20090130797A1 METHODS OF FORMING PHASE-CHANGEABLE MEMORY DEVICES USING GROWTH-ENHANCING AND GROWTH-INHIBITING LAYERS FOR PHASE-CHANGEABLE MATERIALS 失效
标题翻译：使用生长增强和生长抑制层形成可更换材料的相变可变存储器件的方法
公开(公告)号：US20090130797A1
公开(公告)日：2009-05-21
申请号：US12039370
申请日：2008-02-28
申请人： Jinil Lee , Suk Ho Joo , Dohyung Kim , Hyunjun Sim , Hyeyoung Park , Sunglae Cho , Dong-Hyun Im
发明人： Jinil Lee , Suk Ho Joo , Dohyung Kim , Hyunjun Sim , Hyeyoung Park , Sunglae Cho , Dong-Hyun Im
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1616 , H01L45/1683
摘要： Methods of forming phase-changeable memory devices include techniques to inhibit void formation in phase-changeable materials in order to increase device reliability. These techniques to inhibit void formation use an electrically insulating growth-inhibiting layer to guide the formation of a phase-changeable material region within a memory cell (e.g., PRAM cell). In particular, methods of forming an integrated circuit memory device include forming an interlayer insulating layer having an opening therein, on a substrate, and then lining sidewalls of the opening with a seed layer (i.e., growth-enhancing layer) that supports growth of a phase-changeable material thereon. An electrically insulating growth-inhibiting layer is then selectively formed on a portion of the interlayer insulating layer surrounding the opening. The formation of the growth-inhibiting layer is followed by a step to selectively grow a phase-changeable material region in the opening, but not on the growth-inhibiting layer.
摘要翻译：形成相变存储器件的方法包括抑制相变材料中的空隙形成的技术，以增加器件的可靠性。抑制空隙形成的这些技术使用电绝缘的生长抑制层来引导存储单元（例如，PRAM单元）内的相变材料区域的形成。特别地，形成集成电路存储器件的方法包括在衬底上形成其中具有开口的层间绝缘层，然后用支撑生长的种子层（即生长增强层）来衬套开口的侧壁相变材料。然后在围绕开口的层间绝缘层的一部分上选择性地形成电绝缘的生长抑制层。生长抑制层的形成之后是选择性地生长开口中的相变材料区域，而不是在生长抑制层上生长的步骤。

3. 发明申请

US20080061334A1 Semiconductor memory device and method for forming the same 审中-公开
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US20080061334A1
公开(公告)日：2008-03-13
申请号：US11896952
申请日：2007-09-07
申请人： Ju-Young Jung , Suk-Ho Joo , Jung-Hoon Park , Heung-Jin Joo , Hee-San Kim , Seung-Kuk Kang , Do-Yeon Choi
发明人： Ju-Young Jung , Suk-Ho Joo , Jung-Hoon Park , Heung-Jin Joo , Hee-San Kim , Seung-Kuk Kang , Do-Yeon Choi
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L27/11507 , H01L21/76849 , H01L21/7687 , H01L23/5226 , H01L27/11502 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device and a method for forming the same. The method includes forming an insulating layer on a semiconductor substrate having a conductive region, forming a contact hole that exposes the conductive region by etching the insulating layer, forming a barrier metal layer that covers a sidewall and a bottom of the contact hole, and forming a contact plug in the contact hole by interposing the barrier metal layer therebetween. An etching process may be preformed that recesses the barrier metal layer and the contact plug in such a manner that a top surface of the contact plug protrudes upward beyond a top surface of the barrier metal layer. A capping plug may be formed covering the recessed barrier metal layer and the recessed contact plug. A capacitor may be formed on the capping plug.
摘要翻译：一种半导体存储器件及其形成方法。该方法包括在具有导电区域的半导体衬底上形成绝缘层，形成通过蚀刻绝缘层而暴露导电区域的接触孔，形成覆盖接触孔的侧壁和底部的阻挡金属层，以及形成通过在其间插入阻挡金属层，在接触孔中形成接触塞。可以进行蚀刻工艺，其以使得接触插头的顶表面向上突出超过阻挡金属层的顶表面的方式使阻挡金属层和接触插塞凹陷。可以形成覆盖凹陷的阻挡金属层和凹入的接触插塞的封盖塞。可以在封盖上形成电容器。

4. 发明授权

US08557661B2 Methods of manufacturing a semiconductor device and a semiconductor memory device thereby 有权
标题翻译：因此制造半导体器件和半导体存储器件的方法
公开(公告)号：US08557661B2
公开(公告)日：2013-10-15
申请号：US13314627
申请日：2011-12-08
申请人： Han-Geun Yu , Gyung-Jin Min , Seong-Soo Lee , Suk-Ho Joo , Yoo-Chul Kong , Dae-Hyun Jang
发明人： Han-Geun Yu , Gyung-Jin Min , Seong-Soo Lee , Suk-Ho Joo , Yoo-Chul Kong , Dae-Hyun Jang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/11565 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L27/11575 , H01L27/11582
摘要： A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.
摘要翻译：一种制造半导体器件的方法包括在存储单元区域上形成存储单元，在连接区域上交替地形成牺牲层和绝缘中间层，以提供配置为电连接存储单元的布线，形成包括蚀刻掩模图案在顶部牺牲层上的元件，在每个蚀刻掩模图案元件的每个侧壁上形成阻挡侧壁，形成第一光致抗蚀剂图案，选择性地将第一阻挡侧壁从存储器单元区域最远地覆盖并覆盖其它阻挡侧壁，蚀刻暴露顶部牺牲层和绝缘中间层以暴露第二牺牲层，通过横向去除第一光致抗蚀剂图案至第二阻挡侧壁暴露的程度形成第二光致抗蚀剂图案，并将暴露的顶部和第二牺牲层和绝缘夹层蚀刻到形成一个楼梯形状 d侧边缘部分。

5. 发明申请

US20120187471A1 METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR MEMORY DEVICE THEREBY 有权
标题翻译：制造半导体器件的方法和半导体存储器件
公开(公告)号：US20120187471A1
公开(公告)日：2012-07-26
申请号：US13314627
申请日：2011-12-08
申请人： Han-Geun YU , Gyung-Jin MIN , Seong-Soo LEE , Suk-Ho JOO , Yoo-Chul KONG , Dae-Hyun JANG
发明人： Han-Geun YU , Gyung-Jin MIN , Seong-Soo LEE , Suk-Ho JOO , Yoo-Chul KONG , Dae-Hyun JANG
IPC分类号： H01L29/78 , H01L21/336 , H01L21/308
CPC分类号： H01L27/11565 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L27/11575 , H01L27/11582
摘要： A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.
摘要翻译：一种制造半导体器件的方法包括在存储单元区域上形成存储单元，在连接区域上交替地形成牺牲层和绝缘中间层，以提供配置为电连接存储单元的布线，形成包括蚀刻掩模图案在顶部牺牲层上的元件，在每个蚀刻掩模图案元件的每个侧壁上形成阻挡侧壁，形成第一光致抗蚀剂图案，选择性地将第一阻挡侧壁从存储器单元区域最远地覆盖并覆盖其它阻挡侧壁，蚀刻暴露顶部牺牲层和绝缘中间层以暴露第二牺牲层，通过横向去除第一光致抗蚀剂图案至第二阻挡侧壁暴露的程度形成第二光致抗蚀剂图案，并将暴露的顶部和第二牺牲层和绝缘夹层蚀刻到形成一个楼梯形状 d侧边缘部分。

6. 发明授权

US07419881B2 Phase changeable memory device and method of formation thereof 有权
标题翻译：相变存储器件及其形成方法
公开(公告)号：US07419881B2
公开(公告)日：2008-09-02
申请号：US11252807
申请日：2005-10-18
申请人： Byeong-Ok Cho , Suk-Ho Joo , Kyung-Chang Ryoo , Kyung-Rae Byun
发明人： Byeong-Ok Cho , Suk-Ho Joo , Kyung-Chang Ryoo , Kyung-Rae Byun
IPC分类号： H01L21/20
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666
摘要： In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to contact the lower electrode pattern and the interlayer insulating layer; and an upper electrode on the phase changeable pattern.
摘要翻译：在相变存储器件及其形成方法中，相变存储器件包括：层间绝缘层上的下电极图案; 位于下电极图案上的绝缘图案; 穿过绝缘图案和下电极图案的相变图案接触下电极图案和层间绝缘层; 和相位可变图案上的上电极。

7. 发明授权

US07397092B2 Phase changable memory device structures 有权
标题翻译：相变存储器件结构
公开(公告)号：US07397092B2
公开(公告)日：2008-07-08
申请号：US11364950
申请日：2006-03-01
申请人： Hideki Horii , Suk-Ho Joo , Ji-Hye Yi
发明人： Hideki Horii , Suk-Ho Joo , Ji-Hye Yi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/143 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.
摘要翻译：可相变存储器件可以包括衬底，衬底上的绝缘层，第一和第二电极以及第一和第二电极之间的相变材料的图案。更具体地，绝缘层可以在其中具有孔，并且第一电极可以在绝缘层中的孔中。此外，第二电极的部分可以延伸超过相变材料图案的边缘。还讨论了相关方法。

8. 发明申请

US20060110888A1 Phase changeable memory device and method of formation thereof 有权
标题翻译：相变存储器件及其形成方法
公开(公告)号：US20060110888A1
公开(公告)日：2006-05-25
申请号：US11252807
申请日：2005-10-18
申请人： Byeong-Ok Cho , Suk-Ho Joo , Kyung-Chang Ryoo , Kyung-Rae Byun
发明人： Byeong-Ok Cho , Suk-Ho Joo , Kyung-Chang Ryoo , Kyung-Rae Byun
IPC分类号： H01L21/20 , H01L21/8244
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666
摘要： In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to contact the lower electrode pattern and the interlayer insulating layer; and an upper electrode on the phase changeable pattern.
摘要翻译：在相变存储器件及其形成方法中，相变存储器件包括：层间绝缘层上的下电极图案; 位于下电极图案上的绝缘图案; 穿过绝缘图案和下电极图案的相变图案接触下电极图案和层间绝缘层; 和相位可变图案上的上电极。

9. 发明授权

US5843818A Methods of fabricating ferroelectric capacitors 失效
标题翻译：铁电电容器的制造方法
公开(公告)号：US5843818A
公开(公告)日：1998-12-01
申请号：US760576
申请日：1996-12-03
申请人： Suk-ho Joo , Jong Moon
发明人： Suk-ho Joo , Jong Moon
IPC分类号： H01L21/28 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10852 , H01L28/55 , H01L28/91
摘要： Methods of producing ferroelectric capacitors where the electrodes are formed in a contact hole. These methods include the steps of forming an insulating layer on an integrated circuit substrate. A contact hole is then formed through the insulating layer layer to expose a region of the integrated circuit substrate and to define a storage node pattern. A layer of oxidation-resistant conductive material is formed in the contact hole and the insulating layer removed to define a first storage electrode by exposing the layer of oxidation-resistant conductive material. A ferroelectric layer is then formed on the first storage electrode and a second storage electrode is formed on the ferroelectric layer opposite the first storage electrode.
摘要翻译：制造在接触孔中形成电极的铁电电容器的方法。这些方法包括在集成电路基板上形成绝缘层的步骤。然后通过绝缘层层形成接触孔以暴露集成电路衬底的区域并限定存储节点图案。在接触孔中形成抗氧化导电材料层，并且通过暴露耐氧化导电材料层去除绝缘层以限定第一存储电极。然后在第一存储电极上形成铁电层，并且在与第一存储电极相对的铁电层上形成第二存储电极。

10. 发明授权

US08236682B2 Method of forming contact structure 有权
标题翻译：形成接触结构的方法
公开(公告)号：US08236682B2
公开(公告)日：2012-08-07
申请号：US12750157
申请日：2010-03-30
申请人： Kyung-Rae Byun , Suk-Ho Joo , Min-Joon Park
发明人： Kyung-Rae Byun , Suk-Ho Joo , Min-Joon Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76879 , H01L21/76823 , H01L21/76843 , H01L21/76867 , H01L21/76876 , H01L2221/1094 , Y10S977/742 , Y10S977/936
摘要： Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially exposing the conductive pattern. An oxide layer is formed on substantially the entire surface of the substrate on which the opening is formed. A reduction process is performed to reduce the oxide layer. Here, the oxide layer on a bottom region of the opening is reduced to a catalyst layer, and the oxide layer on a region other than the bottom region of the opening is reduced to a non-catalyst layer. A nano material is grown from the catalyst layer, so that a contact plug is formed in the opening.
摘要翻译：提供一种形成接触结构的方法。该方法包括在衬底上形成导电图案。形成覆盖导电图案的层间绝缘层。图案化层间绝缘层以形成部分地暴露导电图案的开口。在其上形成有开口的基板的整个表面上形成氧化物层。进行还原处理以减少氧化物层。这里，开口底部的氧化物层被还原为催化剂层，除开口底部以外的区域的氧化物层还原为非催化剂层。从催化剂层生长纳米材料，使得在开口中形成接触塞。

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