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1. 发明授权

US07419881B2 Phase changeable memory device and method of formation thereof 有权
标题翻译：相变存储器件及其形成方法
公开(公告)号：US07419881B2
公开(公告)日：2008-09-02
申请号：US11252807
申请日：2005-10-18
申请人： Byeong-Ok Cho , Suk-Ho Joo , Kyung-Chang Ryoo , Kyung-Rae Byun
发明人： Byeong-Ok Cho , Suk-Ho Joo , Kyung-Chang Ryoo , Kyung-Rae Byun
IPC分类号： H01L21/20
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666
摘要： In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to contact the lower electrode pattern and the interlayer insulating layer; and an upper electrode on the phase changeable pattern.
摘要翻译：在相变存储器件及其形成方法中，相变存储器件包括：层间绝缘层上的下电极图案; 位于下电极图案上的绝缘图案; 穿过绝缘图案和下电极图案的相变图案接触下电极图案和层间绝缘层; 和相位可变图案上的上电极。

2. 发明申请

US20060110888A1 Phase changeable memory device and method of formation thereof 有权
标题翻译：相变存储器件及其形成方法
公开(公告)号：US20060110888A1
公开(公告)日：2006-05-25
申请号：US11252807
申请日：2005-10-18
申请人： Byeong-Ok Cho , Suk-Ho Joo , Kyung-Chang Ryoo , Kyung-Rae Byun
发明人： Byeong-Ok Cho , Suk-Ho Joo , Kyung-Chang Ryoo , Kyung-Rae Byun
IPC分类号： H01L21/20 , H01L21/8244
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666
摘要： In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to contact the lower electrode pattern and the interlayer insulating layer; and an upper electrode on the phase changeable pattern.
摘要翻译：在相变存储器件及其形成方法中，相变存储器件包括：层间绝缘层上的下电极图案; 位于下电极图案上的绝缘图案; 穿过绝缘图案和下电极图案的相变图案接触下电极图案和层间绝缘层; 和相位可变图案上的上电极。

3. 发明授权

US08026543B2 Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same 有权
标题翻译：具有相变存储单元的半导体器件，使用该半导体器件的电子系统及其制造方法
公开(公告)号：US08026543B2
公开(公告)日：2011-09-27
申请号：US12338814
申请日：2008-12-18
申请人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
发明人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC分类号： H01L27/108 , H01L47/00
CPC分类号： H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
摘要： A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material pattern, and an oxidation barrier of electrically insulative material. The molding layer has a protrusion at its upper portion. One portion of the phase-changeable material pattern overlies the protrusion of the molding layer, and another portion of the phase-changeable material pattern extends through the protrusion. The electrically insulative material of the oxidation barrier may cover the phase-changeable material pattern and/or extend along and cover the entire area at which the protrusion of the molding layer and the portion of the phase-change material pattern disposed on the protrusion adjoin.
摘要翻译：相变存储器件具有氧化阻挡层以防止存储器细胞污染或氧化。在一个实施例中，半导体存储器件包括设置在半导体衬底上的成型层，相变材料图案和电绝缘材料的氧化屏障。成型层在其上部具有突出部。可相变材料图案的一部分覆盖模制层的突起，并且相变材料图案的另一部分延伸穿过突出部。氧化屏障的电绝缘材料可以覆盖相变材料图案和/或延伸并且覆盖模制层的突起和设置在突起上的相变材料图案的部分邻接的整个区域。

4. 发明授权

US07977662B2 Phase-changeable memory devices having reduced susceptibility to thermal interference 有权
标题翻译：相变型存储器件具有降低的对热干扰的敏感性
公开(公告)号：US07977662B2
公开(公告)日：2011-07-12
申请号：US12265262
申请日：2008-11-05
申请人： Kyung-Chang Ryoo , Jong-Woo Ko , Yoon-Jong Song
发明人： Kyung-Chang Ryoo , Jong-Woo Ko , Yoon-Jong Song
IPC分类号： H01L29/06 , H01L47/00
CPC分类号： H01L45/143 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , Y10S257/903
摘要： A non-volatile memory array includes an array of phase-changeable memory elements that are electrically insulated from each other by at least a first electrically insulating region extending between the array of phase-changeable memory elements. The first electrically insulating region includes a plurality of voids therein. Each of these voids extends between a corresponding pair of phase-changeable memory cells in the non-volatile memory array and, collectively, the voids form an array of voids in the first electrically insulating region.
摘要翻译：非易失性存储器阵列包括相变存储元件的阵列，它们通过在可相变存储元件阵列之间延伸的至少第一电绝缘区域彼此电绝缘。第一电绝缘区域中包括多个空隙。这些空隙中的每一个在非易失性存储器阵列中相应的一对相位可变存储单元之间延伸，并且总体上空隙在第一电绝缘区域中形成一组空隙。

5. 发明申请

US20100144090A1 PHASE CHANGE MEMORY DEVICES HAVING DUAL LOWER ELECTRODES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有双下电极的相变存储器件及其制造方法
公开(公告)号：US20100144090A1
公开(公告)日：2010-06-10
申请号：US12709536
申请日：2010-02-22
申请人： Yoon-Jong Song , Kyung-Chang Ryoo , Dong-Won Lim
发明人： Yoon-Jong Song , Kyung-Chang Ryoo , Dong-Won Lim
IPC分类号： H01L21/02
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/1675
摘要： A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.
摘要翻译：半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。包括通过下层间绝缘层并露出衬底的开口。掩埋绝缘图案设置在开口中。依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。包括相变材料图案，其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。包括导电塞，其穿过上层间绝缘层并电连接到相变材料图案。还提供了制造半导体器件的方法。

6. 发明申请

US20090230376A1 RESISTIVE MEMORY DEVICES 有权
标题翻译：电阻式存储器件
公开(公告)号：US20090230376A1
公开(公告)日：2009-09-17
申请号：US12273140
申请日：2008-11-18
申请人： Kyung-Chang Ryoo , Jae-Hee Oh , Jung-Hoon Park , Hyeong-Jun Kim , Dong-Won Lim
发明人： Kyung-Chang Ryoo , Jae-Hee Oh , Jung-Hoon Park , Hyeong-Jun Kim , Dong-Won Lim
IPC分类号： H01L47/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144
摘要： Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. In an embodiment, a bit line is formed of copper using a damascene technique, and when the copper bit line, a copper stud may be formed around the copper bit line
摘要翻译：提供了可以以高集成度密度集成的电阻式存储器件及其形成方法。在一个实施例中，使用大马士革技术由铜形成位线，并且当铜位线可以在铜位线周围形成铜螺柱

7. 发明授权

US08384060B2 Resistive memory device 有权
标题翻译：电阻式存储器件
公开(公告)号：US08384060B2
公开(公告)日：2013-02-26
申请号：US12273140
申请日：2008-11-18
申请人： Kyung-Chang Ryoo , Jae-Hee Oh , Jung-Hoon Park , Hyeong-Jun Kim , Dong-Won Lim
发明人： Kyung-Chang Ryoo , Jae-Hee Oh , Jung-Hoon Park , Hyeong-Jun Kim , Dong-Won Lim
IPC分类号： H01L47/00 , H01L29/06 , H01L21/02 , H01L21/336 , G11C11/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144
摘要： Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. In an embodiment, a bit line is formed of copper using a damascene technique, and when the copper bit line, a copper stud may be formed around the copper bit line.
摘要翻译：提供了可以以高集成度密度集成的电阻式存储器件及其形成方法。在一个实施例中，使用大马士革技术由铜形成位线，并且当铜位线可以围绕铜位线形成铜螺柱时。

8. 发明授权

US07482616B2 Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same 有权
标题翻译：具有相变存储单元的半导体器件，使用该半导体器件的电子系统及其制造方法
公开(公告)号：US07482616B2
公开(公告)日：2009-01-27
申请号：US11139283
申请日：2005-05-27
申请人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
发明人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC分类号： H01L29/02
CPC分类号： H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
摘要： In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.
摘要翻译：在一个实施例中，相变存储器件具有防止存储器单元污染或氧化的氧化阻挡层及其制造方法。在一个实施例中，半导体存储器件包括覆盖半导体衬底的成型层。模制层具有从其顶表面垂直延伸的突出部分。该装置还包括与突出部分相邻的相变材料图案和与相变材料图案电连接的下部电极。

9. 发明授权

US08164079B2 Phase change memory 有权
标题翻译：相变记忆
公开(公告)号：US08164079B2
公开(公告)日：2012-04-24
申请号：US13092725
申请日：2011-04-22
申请人： Yoon-Jong Song , Byung-Seo Kim , Kyung-Chang Ryoo
发明人： Yoon-Jong Song , Byung-Seo Kim , Kyung-Chang Ryoo
IPC分类号： H01L47/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144
摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.
摘要翻译：制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。

10. 发明申请

US20110193047A1 PHASE CHANGE MEMORY 有权
标题翻译：相变记忆
公开(公告)号：US20110193047A1
公开(公告)日：2011-08-11
申请号：US13092725
申请日：2011-04-22
申请人： Yoon-Jong SONG , Byung-Seo Kim , Kyung-Chang Ryoo
发明人： Yoon-Jong SONG , Byung-Seo Kim , Kyung-Chang Ryoo
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144
摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.
摘要翻译：制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。

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