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1. 发明授权

US08236682B2 Method of forming contact structure 有权
标题翻译：形成接触结构的方法
公开(公告)号：US08236682B2
公开(公告)日：2012-08-07
申请号：US12750157
申请日：2010-03-30
申请人： Kyung-Rae Byun , Suk-Ho Joo , Min-Joon Park
发明人： Kyung-Rae Byun , Suk-Ho Joo , Min-Joon Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76879 , H01L21/76823 , H01L21/76843 , H01L21/76867 , H01L21/76876 , H01L2221/1094 , Y10S977/742 , Y10S977/936
摘要： Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially exposing the conductive pattern. An oxide layer is formed on substantially the entire surface of the substrate on which the opening is formed. A reduction process is performed to reduce the oxide layer. Here, the oxide layer on a bottom region of the opening is reduced to a catalyst layer, and the oxide layer on a region other than the bottom region of the opening is reduced to a non-catalyst layer. A nano material is grown from the catalyst layer, so that a contact plug is formed in the opening.
摘要翻译：提供一种形成接触结构的方法。该方法包括在衬底上形成导电图案。形成覆盖导电图案的层间绝缘层。图案化层间绝缘层以形成部分地暴露导电图案的开口。在其上形成有开口的基板的整个表面上形成氧化物层。进行还原处理以减少氧化物层。这里，开口底部的氧化物层被还原为催化剂层，除开口底部以外的区域的氧化物层还原为非催化剂层。从催化剂层生长纳米材料，使得在开口中形成接触塞。

2. 发明授权

US07419881B2 Phase changeable memory device and method of formation thereof 有权
标题翻译：相变存储器件及其形成方法
公开(公告)号：US07419881B2
公开(公告)日：2008-09-02
申请号：US11252807
申请日：2005-10-18
申请人： Byeong-Ok Cho , Suk-Ho Joo , Kyung-Chang Ryoo , Kyung-Rae Byun
发明人： Byeong-Ok Cho , Suk-Ho Joo , Kyung-Chang Ryoo , Kyung-Rae Byun
IPC分类号： H01L21/20
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666
摘要： In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to contact the lower electrode pattern and the interlayer insulating layer; and an upper electrode on the phase changeable pattern.
摘要翻译：在相变存储器件及其形成方法中，相变存储器件包括：层间绝缘层上的下电极图案; 位于下电极图案上的绝缘图案; 穿过绝缘图案和下电极图案的相变图案接触下电极图案和层间绝缘层; 和相位可变图案上的上电极。

3. 发明申请

US20060110888A1 Phase changeable memory device and method of formation thereof 有权
标题翻译：相变存储器件及其形成方法
公开(公告)号：US20060110888A1
公开(公告)日：2006-05-25
申请号：US11252807
申请日：2005-10-18
申请人： Byeong-Ok Cho , Suk-Ho Joo , Kyung-Chang Ryoo , Kyung-Rae Byun
发明人： Byeong-Ok Cho , Suk-Ho Joo , Kyung-Chang Ryoo , Kyung-Rae Byun
IPC分类号： H01L21/20 , H01L21/8244
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666
摘要： In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to contact the lower electrode pattern and the interlayer insulating layer; and an upper electrode on the phase changeable pattern.
摘要翻译：在相变存储器件及其形成方法中，相变存储器件包括：层间绝缘层上的下电极图案; 位于下电极图案上的绝缘图案; 穿过绝缘图案和下电极图案的相变图案接触下电极图案和层间绝缘层; 和相位可变图案上的上电极。

4. 发明申请

US20060273366A1 Methods of manufacturing ferroelectric capacitors and semiconductor devices 审中-公开
标题翻译：制造铁电电容器和半导体器件的方法
公开(公告)号：US20060273366A1
公开(公告)日：2006-12-07
申请号：US11447545
申请日：2006-06-06
申请人： Hwa-Young Ko , Suk-Ho Joo , Byoung-Jae Bae , Hee-Seok Kim , Kyung-Rae Byun , Jin-Hwan Ham
发明人： Hwa-Young Ko , Suk-Ho Joo , Byoung-Jae Bae , Hee-Seok Kim , Kyung-Rae Byun , Jin-Hwan Ham
IPC分类号： H01L29/94
CPC分类号： H01L28/55 , H01L21/32139 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： In a method of manufacturing a ferroelectric capacitor, a lower electrode layer is formed on a substrate. The lower electrode layer includes at least one lower electrode film. A ferroelectric layer is formed on the lower electrode layer, and then an upper electrode layer is formed on the ferroelectric layer. A hard mask structure is formed on the upper electrode layer. The hard mask structure includes a first hard mask and a second hard mask. An upper electrode, a ferroelectric layer pattern and a lower electrode are formed by partially etching the upper electrode layer, the ferroelectric layer and the lower electrode layer using the hard mask structure. The hard mask structure may prevent damage to the ferroelectric layer and may enlarge an effective area of the ferroelectric capacitor so that the ferroelectric capacitor may have enhanced electrical and ferroelectric characteristics.
摘要翻译：在制造铁电电容器的方法中，在基板上形成下电极层。下电极层包括至少一个下电极膜。在下电极层上形成铁电体层，在铁电层上形成上电极层。在上电极层上形成硬掩模结构。硬掩模结构包括第一硬掩模和第二硬掩模。通过使用硬掩模结构部分蚀刻上电极层，铁电层和下电极层，形成上电极，铁电层图案和下电极。硬掩模结构可以防止对铁电层的损坏，并且可以增加铁电电容器的有效面积，使得铁电电容器可以具有增强的电和铁电特性。

5. 发明授权

US07494866B2 Semiconductor device and related method of manufacture 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US07494866B2
公开(公告)日：2009-02-24
申请号：US11403901
申请日：2006-04-14
申请人： Hwa-Young Ko , Kyung-Rae Byun , Hyoung-Seub Rhie , Hee-Seok Kim , Jin-Hwan Ham , Suk-Ho Joo
发明人： Hwa-Young Ko , Kyung-Rae Byun , Hyoung-Seub Rhie , Hee-Seok Kim , Jin-Hwan Ham , Suk-Ho Joo
IPC分类号： H01L21/8242
CPC分类号： H01L23/485 , H01L27/105 , H01L27/11502 , H01L27/11507 , H01L27/11509 , H01L28/55 , H01L28/65 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are a semiconductor device and a related method of manufacture. The semiconductor device comprises a semiconductor substrate, a conductive structure including contact regions and gate structures formed on the semiconductor substrate, a protection layer formed on the gate structures, an insulation layer formed on the protection layer, and a plurality of contacts directly contacting the contact regions and the semiconductor substrate through the insulation layer, wherein the contacts have substantially different heights from each other.
摘要翻译：公开了半导体器件和相关的制造方法。半导体器件包括半导体衬底，包括形成在半导体衬底上的接触区域和栅极结构的导电结构，形成在栅极结构上的保护层，形成在保护层上的绝缘层，以及直接接触触点的多个触点区域和半导体衬底通过绝缘层，其中触点彼此具有实质上不同的高度。

6. 发明申请

US20060237851A1 Semiconductor device and related method of manufacture 有权
公开(公告)号：US20060237851A1
公开(公告)日：2006-10-26
申请号：US11403901
申请日：2006-04-14
申请人： Hwa-Young Ko , Kyung-Rae Byun , Hyoung-Seub Rhie , Hee-Seok Kim , Jin-Hwan Ham , Suk-Ho Joo
发明人： Hwa-Young Ko , Kyung-Rae Byun , Hyoung-Seub Rhie , Hee-Seok Kim , Jin-Hwan Ham , Suk-Ho Joo
IPC分类号： H01L23/52
CPC分类号： H01L23/485 , H01L27/105 , H01L27/11502 , H01L27/11507 , H01L27/11509 , H01L28/55 , H01L28/65 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are a semiconductor device and a related method of manufacture. The semiconductor device comprises a semiconductor substrate, a conductive structure including contact regions and gate structures formed on the semiconductor substrate, a protection layer formed on the gate structures, an insulation layer formed on the protection layer, and a plurality of contacts directly contacting the contact regions and the semiconductor substrate through the insulation layer, wherein the contacts have substantially different heights from each other.

7. 发明申请

US20080182408A1 Methods of Forming Carbon Nano-Tube Wires on a Catalyst Metal Layer and Related Methods of Wiring Semiconductor Devices Using Such Carbon Nano-Tube Wires 审中-公开
标题翻译：在催化剂金属层上形成碳纳米管线的方法和使用这种碳纳米管线的半导体器件接线的相关方法
公开(公告)号：US20080182408A1
公开(公告)日：2008-07-31
申请号：US11842415
申请日：2007-08-21
申请人： Sun-Woo Lee , In-Seok Yeo , Jun-Young Lee , Jung-Hyeon Kim , Hong-Sik Yoon , Kyung-Rae Byun
发明人： Sun-Woo Lee , In-Seok Yeo , Jun-Young Lee , Jung-Hyeon Kim , Hong-Sik Yoon , Kyung-Rae Byun
IPC分类号： H01L21/768
CPC分类号： H01L21/76814 , H01L21/76823 , H01L21/76829 , H01L21/76876 , H01L21/76879 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/1683 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a carbon nano-tube, an oxidized metal layer is formed on a substrate. An insulation layer having an opening is formed on the oxidized metal layer to expose a surface of the oxidized metal layer through the opening. The oxidized metal layer exposed through the opening is converted into a catalyst metal layer pattern for allowing a carbon nano-tube to grow from the catalyst metal layer pattern. The carbon nano-tube grows from the catalyst metal layer pattern to form a carbon nano-tube wire in the opening. Thus, the carbon nano-tube may not grow between the insulation layer pattern and the catalyst metal layer pattern.
摘要翻译：在形成碳纳米管的方法中，在基板上形成氧化金属层。在氧化金属层上形成具有开口的绝缘层，以通过开口露出氧化金属层的表面。通过开口暴露的氧化金属层被转化为催化剂金属层图案，以使碳纳米管从催化剂金属层图案生长。碳纳米管从催化剂金属层图案生长，以在开口中形成碳纳米管丝。因此，碳纳米管可能不会在绝缘层图案和催化剂金属层图案之间生长。

8. 发明授权

US07585718B2 Method of manufacturing a carbon nano-tube transistor 失效
标题翻译：制造碳纳米管晶体管的方法
公开(公告)号：US07585718B2
公开(公告)日：2009-09-08
申请号：US11932994
申请日：2007-10-31
申请人： Hong Cho , Seung-Pil Chung , Hong Sik Yoon , Kyung-Rae Byun
发明人： Hong Cho , Seung-Pil Chung , Hong Sik Yoon , Kyung-Rae Byun
IPC分类号： H01L21/336 , H01L21/335
CPC分类号： H01L51/057 , B82Y10/00 , H01L51/0048 , Y10T29/49105
摘要： A multilayer insulating structure including a first stop layer, a first insulating layer and a second stop layer is formed on the first conductive structure. A second conductive structure and a second insulating layer are formed on the first conductive structure. The second insulating layer and the second conductive structure are etched to form a first hole and a second hole having a first radius. A spacer is formed on sidewalls of the first and second holes. The second stop layer and the first insulating layer are etched using the spacer as an etch mask to form a third hole having a second radius smaller than the first radius. A sacrificial filler is formed on the first stop layer to fill the third hole. After removing the spacer, the sacrificial filler is removed. The first stop layer is etched. A carbon nano-tube is grown from the first conductive structure.
摘要翻译：在第一导电结构上形成包括第一阻挡层，第一绝缘层和第二阻挡层的多层绝缘结构。在第一导电结构上形成第二导电结构和第二绝缘层。蚀刻第二绝缘层和第二导电结构以形成具有第一半径的第一孔和第二孔。间隔件形成在第一孔和第二孔的侧壁上。使用间隔物作为蚀刻掩模蚀刻第二阻挡层和第一绝缘层，以形成具有小于第一半径的第二半径的第三孔。在第一停止层上形成牺牲填料以填充第三孔。去除间隔物后，去除牺牲填料。第一个停止层被蚀刻。从第一导电结构生长碳纳米管。

9. 发明申请

US20080016675A1 Methods of Forming Magnetic Memory Devices Including Ferroelectric Spacers 有权
标题翻译：形成包含铁电隔离器的磁存储器件的方法
公开(公告)号：US20080016675A1
公开(公告)日：2008-01-24
申请号：US11776625
申请日：2007-07-12
申请人： Kyung-Rae Byun , Sung-Lae Cho
发明人： Kyung-Rae Byun , Sung-Lae Cho
IPC分类号： H01F7/06 , G11B5/127 , H05K3/10
CPC分类号： H01L43/12 , G11C11/16 , H01L27/228 , H01L43/08 , Y10T29/49043 , Y10T29/49044 , Y10T29/49046 , Y10T29/49048 , Y10T29/49052 , Y10T29/49155
摘要： A magnetic memory device may include a digit line on a substrate, a first insulating layer on the digit line, and a magnetic tunnel junction memory cell on the first insulating layer so that the first insulating layer is between the digit line and the magnetic tunnel junction memory cell. A second insulating layer may be provided on the magnetic tunnel junction memory cell, wherein the second insulating layer has a hole therein exposing portions of the magnetic tunnel junction memory cell. A bit line may be provided on the second insulating layer and on portions of the magnetic tunnel junction memory cell exposed by the hole in the second insulating layer, and ferromagnetic spacers may be provided on sidewalls of at least one of the digit line and/or the bit line. Related methods are also discussed.
摘要翻译：磁存储器件可以包括衬底上的数字线，数字线上的第一绝缘层和第一绝缘层上的磁性隧道结存储单元，使得第一绝缘层位于数字线和磁性隧道结之间记忆单元第二绝缘层可以设置在磁性隧道结存储单元上，其中第二绝缘层在其中具有一个孔，暴露出磁性隧道结存储单元的部分。位线可以设置在第二绝缘层上以及在由第二绝缘层中的孔暴露的磁性隧道结存储单元的部分上，并且铁磁间隔物可以设置在数字线和/或其中的至少一个的侧壁上位线。还讨论了相关方法。

10. 发明申请

US20060022237A1 Magnetic memory devices including ferroelectric spacers and related methods 审中-公开
标题翻译：包括铁电间隔物和相关方法的磁存储器件
公开(公告)号：US20060022237A1
公开(公告)日：2006-02-02
申请号：US11093206
申请日：2005-03-29
申请人： Kyung-Rae Byun , Sung-Lae Cho
发明人： Kyung-Rae Byun , Sung-Lae Cho
IPC分类号： H01L29/94
CPC分类号： H01L43/12 , G11C11/16 , H01L27/228 , H01L43/08 , Y10T29/49043 , Y10T29/49044 , Y10T29/49046 , Y10T29/49048 , Y10T29/49052 , Y10T29/49155
摘要： A magnetic memory device may include a digit line on a substrate, a first insulating layer on the digit line, and a magnetic tunnel junction memory cell on the first insulating layer so that the first insulating layer is between the digit line and the magnetic tunnel junction memory cell. A second insulating layer may be provided on the magnetic tunnel junction memory cell, wherein the second insulating layer has a hole therein exposing portions of the magnetic tunnel junction memory cell. A bit line may be provided on the second insulating layer and on portions of the magnetic tunnel junction memory cell exposed by the hole in the second insulating layer, and ferromagnetic spacers may be provided on sidewalls of at least one of the digit line and/or the bit line. Related methods are also discussed.
摘要翻译：磁存储器件可以包括衬底上的数字线，数字线上的第一绝缘层和第一绝缘层上的磁性隧道结存储单元，使得第一绝缘层位于数字线和磁性隧道结之间记忆单元第二绝缘层可以设置在磁性隧道结存储单元上，其中第二绝缘层在其中具有一个孔，暴露出磁性隧道结存储单元的部分。位线可以设置在第二绝缘层上以及在由第二绝缘层中的孔暴露的磁性隧道结存储单元的部分上，并且铁磁间隔物可以设置在数字线和/或其中的至少一个的侧壁上位线。还讨论了相关方法。

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